C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 205

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

20.
UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0 may operate
in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor communication is fully sup-
ported. Receive data is buffered in a holding register, allowing UART0 to start reception of a second incoming data
byte before software has finished reading the previous data byte. A Receive Overrun bit indicates when new received
data is latched into the receive buffer before the previous received byte is read.
UART0 is accessed via its associated SFRs, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The single
SBUF0 location provides access to both transmit and receive registers. Reads access the Receive register and writes
access the Transmit register automatically.
UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit Interrupt flag,
TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI0 (SCON0.0) set
when reception of a data byte is complete. UART0 interrupt flags are not cleared by hardware when the CPU vectors
to the interrupt service routine; they must be cleared manually by software. This allows software to determine the
cause of the UART0 interrupt (transmit complete or receive complete).
Generation
Baud Rate
UART0
UART
Logic
Write to
SBUF
Figure 20.1. UART0 Block Diagram
Tx Clock
Rx Clock
Start
Stop Bit
Start
Frame Error
Gen.
Detection
Load SBUF
D
TB8
SET
CLR
(Receive Latch)
Q
Shift
M
S
0
SFR Bus
M
S
1
SBUF
Tx Control
Rx Control
M
S
2
SCON
Shift
Input Shift Register
EN
(Transmit Shift)
R
E
N
Zero Detector
T
B
8
SFR Bus
SBUF
R
B
8
(9 bits)
Tx IRQ
T
I
Rx IRQ
SBUF
Read
R
I
0x1FF
Match Detect
Rev. 1.4
Address
TI
SBUF
Match
RI
Send
Load
Data
RB8
SADDR
SADEN
RX
TX
C8051F020/1/2/3
Crossbar
Crossbar
Serial Port
(UART0/1)
Interrupt
Port I/O
205