C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 208

DEV KIT FOR F020/F021/F022/F023

C8051F020DK

Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F020DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
C8051F020/1/2/3
20.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data
bits (LSB first), a programmable ninth data bit, and a stop bit. Mode 2 supports multiprocessor communications and
hardware address recognition (see
the ninth data bit is determined by the value in TB80 (SCON0.3). It can be assigned the value of the parity flag P in
the PSW or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and
the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt
Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF0 receive register if RI0 is logic 0 and one of the following requirements are met:
If the above conditions are satisfied, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set.
An interrupt will occur if enabled when either TI0 or RI0 is set.
The baud rate in Mode 2 is either SYSCLK / 32 or SYSCLK / 64, depending on the value of the SMOD0 bit in regis-
ter PCON.
208
SPACE
MARK
BIT TIMES
BIT SAMPLING
1.
2.
SM20 is logic 0
SM20 is logic 1, the received 9th bit is logic 1, and the received address matches the UART0 address as
described in
START
BIT
Figure 20.5. UART Modes 2 and 3 Timing Diagram
Section
D0
20.2.
D1
Section “20.2. Multiprocessor Communications” on page
BaudRate
Equation 20.3. Mode 2 Baud Rate
D2
=
D3
2
Rev. 1.4
SMOD0
D4
SYSCLK
--------------------- -
D5
64
D6
D7
210). On transmit,
D8
STOP
BIT

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