C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 235

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

22.1.1. Mode 0: 16-bit Counter/Timer with Capture
In this mode, Timer 2 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the T2EX
input pin causes the following to occur:
Timer 2 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the T2 input pin as its clock
source when operating in Capture mode. Clearing the C/T2 bit (T2CON.1) selects the system clock as the input for
the timer (divided by one or twelve as specified by the Timer Clock Select bit T2M in CKCON). When C/T2 is set to
logic 1, a high-to-low transition at the T2 input pin increments the counter/timer register. As the 16-bit counter/timer
register increments and overflows from 0xFFFF to 0x0000, the TF2 timer overflow flag (T2CON.7) is set and an
interrupt will occur if the interrupt is enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RL2 (T2CON.0) and the
Timer 2 Run Control bit TR2 (T2CON.2) to logic 1. The Timer 2 External Enable EXEN2 (T2CON.3) must also be
set to logic 1 to enable a capture. If EXEN2 is cleared, transitions on T2EX will be ignored.
SYSCLK
1.
2.
3.
The 16-bit value in Timer 2 (TH2, TL2) is loaded into the capture registers (RCAP2H, RCAP2L).
The Timer 2 External Flag (EXF2) is set to ‘1’.
A Timer 2 interrupt is generated if enabled.
T2EX
T2
12
Crossbar
EXEN2
M
T
4
CKCON
M
0
1
T
2
M
T
1
M
T
0
Figure 22.11. T2 Mode 0 Block Diagram
0
1
TR2
Rev. 1.4
Capture
TCLK
RCAP2L
TL2
C8051F020/1/2/3
RCAP2H
TH2
CP/RL2
EXEN2
TCLK0
RCLK0
EXF2
C/T2
TR2
TF2
Interrupt
235