C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 75

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

7.
The ADC1 subsystem for the C8051F020/1/2/3 consists of an 8-channel, configurable analog multiplexer (AMUX1),
a programmable gain amplifier (PGA1), and a 500 ksps, 8-bit successive-approximation-register ADC with inte-
grated track-and-hold (see block diagram in Figure 7.1). The AMUX1, PGA1, and Data Conversion Modes, are all
configurable under software control via the Special Function Registers shown in Figure 7.1. The ADC1 subsystem
(8-bit ADC, track-and-hold and PGA) is enabled only when the AD1EN bit in the ADC1 Control register (ADC1CN)
is set to logic 1. The ADC1 subsystem is in low power shutdown when this bit is logic 0. The voltage reference used
by ADC1 is selected as described in
C8051F020/2 devices, or
devices.
7.1.
Eight ADC1 channels are available for measurement, as selected by the AMX1SL register (see Figure 7.5). The PGA
amplifies the ADC1 output signal by an amount determined by the states of the AMP1GN2-0 bits in the ADC1 Con-
figuration register, ADC1CF (Figure 7.4). The PGA can be software-programmed for gains of 0.5, 1, 2, or 4. Gain
defaults to 0.5 on reset.
Important Note: AIN1 pins also function as Port 1 I/O pins, and must be configured as analog inputs when used as
ADC1 inputs. To configure an AIN1 pin for analog input, set to ‘0’ the corresponding bit in register P1MDIN. Port 1
pins selected as analog inputs are skipped by the Digital I/O Crossbar. See
as Analog Inputs (AIN1.[7:0])” on page 165
AIN1.0 (P1.0)
AIN1.1 (P1.1)
AIN1.2 (P1.2)
AIN1.3 (P1.3)
AIN1.4 (P1.4)
AIN1.5 (P1.5)
AIN1.6 (P1.6)
AIN1.7 (P1.7)
ADC1 (8-BIT ADC)
Analog Multiplexer and PGA
Section “10. VOLTAGE REFERENCE (C8051F021/3)” on page 93
Figure 7.1. ADC1 Functional Block Diagram
AMUX
8-to-1
AMX1SL
Section “9. VOLTAGE REFERENCE (C8051F020/2)” on page 91
X
for more information on configuring the AIN1 pins.
+
-
AV+
AD1EN
AGND
ADC1CF
Rev. 1.4
ADC
8-Bit
SAR
AV+
ADC1CN
Section “17.1.6. Configuring Port 1 Pins
Start Conversion
C8051F020/1/2/3
8
000
001
010
011
1xx
for C8051F021/3
Write to AD1BUSY
Timer 3 Overflow
CNVSTR
Timer 2 Overflow
Write to AD0BUSY
(synchronized with
ADC0)
75
for