C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 130

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

C8051F410/1/2/3
15.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 15.1 for complete RST pin
specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
15.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
15.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
130
Bit7:
Bit6:
Bit5:
Bits4–0: Reserved. Read = Variable. Write = don’t care.
VDMEN VDDSTAT VDMLVL Reserved Reserved Reserved Reserved Reserved 1v000000
R/W
Bit7
VDMEN: V
This bit turns the V
until it is also selected as a reset source in register RSTSRC (SFR Definition 15.2). The V
Monitor can be allowed to stabilize before it is selected as a reset source. Selecting the
V
See Table 15.1 for the minimum V
0: V
1: V
VDDSTAT: V
This bit indicates the current power supply status (V
0: V
1: V
VDMLVL: V
0: V
1: V
that includes code that writes to and/or erases Flash.
DD
DD
DD
DD
DD
DD
DD
monitor as a reset source before it has stabilized may generate a system reset.
Bit6
R
Monitor Disabled. 
Monitor Enabled (default).
is at or below the V
is above the V
Monitor Threshold is set to V
Monitor Threshold is set to V
SFR Definition 15.1. VDM0CN: V
DD
DD
DD
Monitor Enable.
Level Select.
Status.
R/W
Bit5
DD
DD
monitor circuit on/off. The V
Monitor Threshold.
DD
Bit4
R
Monitor Threshold.
DD
RST-LOW
RST-HIGH
Rev. 1.1
Monitor turn-on time.
Bit3
R
. This setting is recommended for any system
(default).
DD
DD
Bit2
R
DD
Monitor cannot generate system resets
Monitor Control
Monitor output).
Bit1
R
SFR Address:
Bit0
R
0xFF
Reset Value
DD