C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 172

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

C8051F410/1/2/3
19.3. Clock Multiplier
The Clock Multiplier generates an output clock which is 4 times the input clock frequency scaled by a pro-
grammable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7. The Clock Multiplier’s input can be
selected from the external oscillator, or the internal or external oscillators divided by 2. This produces three
possible base outputs which can be scaled by a programmable factor: Internal Oscillator x 2, External
Oscillator x 2, or External Oscillator x 4. See
The Clock Multiplier is configured via the CLKMUL register (SFR Definition 19.4). The procedure for con-
figuring and enabling the Clock Multiplier is as follows:
Important Note: When using an external oscillator as the input to the Clock Multiplier, the external
source must be enabled and stable before the Multiplier is initialized. See
on selecting an external oscillator source.
The Clock Multiplier allows faster operation of the CIP-51 core and is intended to generate an output fre-
quency between 25 and 50 MHz. The clock multiplier can also be used with slow input clocks. However, if
the clock is below the minimum Clock Multiplier input frequency (FCM
erated clock will consist of four fast pulses followed by a long delay until the next input clock rising edge.
The average frequency of the output is equal to 4x the input, but the instantaneous frequency may be
faster. See Figure 19.3 for more information.
172
1. Reset the Multiplier by writing 0x00 to register CLKMUL.
2. Select the Multiplier input source via the MULSEL bits.
3. Select the Multiplier output scaling factor via the MULDIV bits
4. Enable the Multiplier with the MULEN bit (CLKMUL | = 0x80).
5. Delay for >5 µs.
6. Initialize the Multiplier with the MULINIT bit (CLKMUL | = 0xC0).
7. Poll for MULRDY => ‘1’. 
if F
if F
CM
CM
F
F
in
in
F
F
CM
CM
CM
< F
CM
> F
out
out
in
in
CM
CM
Figure 19.3. Example Clock Multiplier Output
min
min
Section 19.4
Rev. 1.1
for details on system clock selection.
min
) specified in Table 19.1, the gen-
Section 19.4
for details