C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 187

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

20.4. Backup Regulator and RAM
The smaRTClock includes a backup supply regulator that keeps the smaRTClock peripheral fully func-
tional when V
which can range from 1 V to 5.25 V. Switchover logic automatically powers smaRTClock from the backup
supply when the voltage at V
The smaRTClock also includes 64 bytes of backup RAM. This memory can be read and written indirectly
using the RAMADDR and RAMDATA internal registers.
Internal Register Definition 20.8. RAMADDR: smaRTClock Backup RAM Address
Bits 7–0: ALARMn: smaRTClock Alarm Target.
Note: The LSB of ALARM0 is not used. The LSB of the 47-bit smaRTClock timer will be compared
Bit 7:
smaRTClock Addresses: ALARM0: 0x08; ALARM1: 0x09; ALARM2: 0x0A; ALARM3: 0x0B; ALARM4: 0x0C; ALARM5: 0x0D
Note: These registers are not SFRs. They can only be accessed indirectly through RTC0ADR and RTC0DAT.
R/W
R/W
Bit7
Bit7
Note: This register is not an SFR. It can only be accessed indirectly through RTC0ADR and RTC0DAT.
These 6 registers (ALARM5–ALARM0) are used to set an alarm event for the smaRTClock
timer. The smaRTClock alarm should be disabled (RTC0AEN=0) when updating these reg-
isters. 
against ALARM0.1.
RAMADDR: smaRTClock Battery Backup RAM Address Bits
These bits select the smaRTClock Backup RAM byte that is targeted by RAMDATA. This
address auto-increments after each read or write of RAMDATA.
Internal Register Definition 20.7. ALARMn: smaRTClock Alarm
DD
R/W
R/W
Bit6
Bit6
is turned off. The backup supply regulator regulates the V
R/W
R/W
Bit5
Bit5
RTC-BACKUP
R/W
R/W
Bit4
Bit4
is greater than V
Rev. 1.1
R/W
R/W
Bit3
Bit3
DD
.
R/W
R/W
Bit2
Bit2
C8051F410/1/2/3
R/W
R/W
Bit1
Bit1
RTC-BACKUP
R/W
R/W
Bit0
Bit0
supply voltage,
smaRTClock
00000000
Reset Value
Reset Value
11111111
Address:
0x0E
187