C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 246

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

C8051F410/1/2/3
24.3.3. External/smaRTClock Capture Mode
Capture Mode allows either the external oscillator or the smaRTClock clock to be measured against the
system clock. The external oscillator and smaRTClock clock can also be compared against each other.
Timer 3 can be clocked from the system clock, the system clock divided by 12, the external oscillator
divided by 8, or the smaRTClock clock divided by 8, depending on the T3ML (CKCON.6), T3XCLK, and
T3RCLK settings. The timer will capture either every 8 external clock cycles or every 8 smaRTClock clock
cycles, depending on the T3RCLK setting. When a capture event is generated, the contents of Timer 3
(TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL) and the TF3H flag is
set. By recording the difference between two successive timer capture values, the external oscillator or
smaRTClock clock can be determined with respect to the Timer 3 clock. The Timer 3 clock should be much
faster than the capture clock to achieve an accurate reading. Timer 3 should be in 16-bit auto-reload mode
when using Capture Mode.
For example, if T3ML = 1b, T3RCLK = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and cap-
ture every smaRTClock clock divided by 8. If the SYSCLK is 24.5 MHz and the difference between two
successive captures is 5984, then the smaRTClock clock is:
24.5 MHz / (5984 / 8) = 0.032754 MHz or 32.754 kHz.
This mode allows software to determine the exact smaRTClock frequency in self-oscillate mode and the
external oscillator frequency when an RC network or capacitor is used to generate the signal.
246
External Osc. / 8
smaRTClock / 8
T3RCLK
1
0
SYSCLK / 12
Figure 24.9. Timer 3 Capture Mode Block Diagram
T3XCLK
1
0
SYSCLK
External Osc. / 8
smaRTClock / 8
M
H
T
3
TF3CEN
M
1
T
3
L
0
CKCON
M
H
T
2
M
T
2
L
M
T
1
M
T
0
TR3
S
C
A
1
Rev. 1.1
S
C
A
0
T3RCLK
1
0
Capture
TCLK
TMR3RLH
TMR3H
TMR3RLL
TMR3L
TF3CEN
T3RCLK
TF3LEN
T3XCLK
TF3H
TF3L
TR3
Interrupt