C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 33

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

1.12. Port Input/Output
C8051F41x devices include up to 24 I/O pins. Port pins are organized as three byte-wide ports. The port
pins behave like typical 8051 ports with a few enhancements. Each port pin can be configured as a digital
or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or open-drain operation. The
“weak pullups” that are fixed on typical 8051 devices may be individually or globally disabled to save
power.
The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip coun-
ter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the
port pins using the Crossbar control registers. This allows the user to select the exact mix of general-pur-
pose port I/O, digital, and analog resources needed for the application.
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
P2
PCA
CP0
CP1
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
Figure 1.11. Port I/O Functional Block Diagram
2
4
2
4
7
2
8
8
8
Rev. 1.1
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
8
8
8
P0MASK, P0MATCH
P1MASK, P1MATCH
C8051F410/1/2/3
Registers
Cells
Cells
Cell
I/O
I/O
I/O
P0
P1
P2
P2.3–2.6 available on
PnMDIN Registers
C8051F410/2
PnMDOUT,
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
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