C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet

DEV KIT FOR F060/F062/F063

C8051F060DK

Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F060DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214
Preliminary Rev. 1.2 7/04
Analog Peripherals
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-
-
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On-Chip JTAG Debug & Boundary Scan
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-
-
-
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Two 16-Bit SAR ADCs
10-bit SAR ADC (C8051F060/1/2/3)
Two 12-bit DACs (C8051F060/1/2/3)
Three Analog Comparators
Voltage Reference
Precision VDD Monitor/Brown-Out Detector
On-chip debug circuitry facilitates full-speed, non-
intrusive in-circuit/in-system debugging
Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
IEEE1149.1 compliant boundary scan
Complete development kit
16-bit resolution
±0.75 LSB INL, guaranteed no missing codes
Programmable throughput up to 1 Msps
Operate as two single-ended or one differential con-
verter
Direct memory access; data stored in RAM without
software overhead
Data-dependent windowed interrupt generator
Programmable throughput up to 200 ksps
8 external inputs, single-ended or differential
Built-in temperature sensor
Can synchronize outputs to timers for jitter-free wave-
form generation
Programmable hysteresis/response time
INTERRUPTS
ANALOG PERIPHERALS
C8051F060/1/2/3 Only
1 Msps
1 Msps
Copyright © 2004 by Silicon Laboratories
8051 CPU
(25MIPS)
16-bit
16-bit
200ksps
ADC
ADC
22
10-bit
HIGH-SPEED CONTROLLER CORE
ADC
VREF
SENSOR
TEMP
Interface
CIRCUITRY
DMA
COMPARATOR
DEBUG
+
-
ISP FLASH
VOLTAGE
64/32 kB
+
-
S
+
-
12-Bit
12-Bit
DAC
DAC
Mixed Signal ISP Flash MCU Family
High Speed 8051 C Core
-
-
-
Memory
-
-
-
Digital Peripherals
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-
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-
Clock Sources
-
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Supply Voltage .......................... 2.7 to 3.6 V
-
100-Pin and 64-Pin TQFP Packages Available
Temperature Range: -40 to +85 °C
C8051F060/1/2/3/4/5/6/7
CIRCUIT
CLOCK
SPI Bus
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
C8051F060/1/2/3
UART0
UART1
SMBus
CAN 2.0B
Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Flexible Interrupt sources
4352 Bytes internal data RAM (4 k + 256)
64 kB (C8051F060/1/2/3/4/5), 32 kB (C8051F066/7)
Flash; In-system programmable in 512-byte sectors
External 64 kB data memory interface with multi-
plexed and non-multiplexed modes (C8051F060/2/
4/6)
59 general purpose I/O pins (C8051F060/2/4/6)
24 general purpose I/O pins (C8051F061/3/5/7)
Bosch Controller Area Network (CAN 2.0B -
C8051F060/1/2/3)
Hardware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
Programmable 16-bit counter/timer array with
6 capture/compare modules
5 general purpose 16-bit counter/timers
Dedicated watchdog timer; bi-directional reset pin
Internal calibrated precision oscillator: 24.5 MHz
External oscillator: Crystal, RC, C, or clock
Multiple power saving sleep and shutdown modes
PCA
4352 B
SRAM
DIGITAL I/O
100 pin Only
CONTROL
SANITY
JTAG
Port 3
Port 4
Port 5
Port 6
Port 7
Port 0
Port 1
Port 2
C8051F060/1/2/3/4/5/6/7

Related parts for C8051F060DK

C8051F060DK Summary of contents

Page 1

Analog Peripherals - Two 16-Bit SAR ADCs • 16-bit resolution • ±0.75 LSB INL, guaranteed no missing codes • Programmable throughput Msps • Operate as two single-ended or one differential con- verter • Direct memory access; data ...

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C8051F060/1/2/3/4/5/6/7 2 Rev. 1.2 ...

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Table of Contents 1. System Overview.................................................................................................... 19 1.1. CIP-51™ Microcontroller Core.......................................................................... 25 1.1.1. Fully 8051 Compatible.............................................................................. 25 1.1.2. Improved Throughput ............................................................................... 25 1.1.3. Additional Features .................................................................................. 26 1.2. On-Chip Memory............................................................................................... 27 1.3. JTAG Debug and Boundary Scan..................................................................... 28 1.4. Programmable ...

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C8051F060/1/2/3/4/5/6/7 7.3. Programmable Window Detector ...................................................................... 97 7.3.1. Window Detector In Single-Ended Mode ................................................. 99 7.3.2. Window Detector In Differential Mode.................................................... 100 8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) .................... 103 8.1. DAC Output Scheduling.................................................................................. 104 8.1.1. Update ...

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WDT ................................................................................ 166 14.7.2.Disable WDT .......................................................................................... 166 14.7.3.Disable WDT Lockout ............................................................................ 166 14.7.4.Setting WDT Interval .............................................................................. 166 15. Oscillators ............................................................................................................. 171 15.1.Programmable Internal Oscillator ................................................................... 171 15.2.External Oscillator Drive Circuit...................................................................... 173 15.3.System Clock Selection.................................................................................. 173 15.4.External Crystal Example ............................................................................... ...

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C8051F060/1/2/3/4/5/6/7 18.1.5.Configuring Port 1 and 2 pins as Analog Inputs..................................... 207 18.1.6.Crossbar Pin Assignment Example........................................................ 208 18.2.Ports 4 through 7 (C8051F060/2/4/6 only) ..................................................... 219 18.2.1.Configuring Ports which are not Pinned Out .......................................... 219 18.2.2.Configuring the Output Modes of the Port ...

Page 7

Clock Timing......................................................................................... 256 21.6.SPI Special Function Registers ...................................................................... 258 22. UART0.................................................................................................................... 265 22.1.UART0 Operational Modes ............................................................................ 266 22.1.1.Mode 0: Synchronous Mode .................................................................. 266 22.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 267 22.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate .................................................. ...

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C8051F060/1/2/3/4/5/6/7 26.2.Flash Programming Commands..................................................................... 322 26.3.Debug Support ............................................................................................... 325 27. Document Change List ........................................................................................ 327 27.1.Revision 1.1 to Revision 1.2 ........................................................................... 327 8 Rev. 1.2 ...

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List of Figures 1. System Overview.................................................................................................... 19 Figure 1.1. C8051F060 / C8051F062 Block Diagram .............................................. 21 Figure 1.2. C8051F061 / C8051F063 Block Diagram .............................................. 22 Figure 1.3. C8051F064 / C8051F066 Block Diagram .............................................. 23 Figure 1.4. C8051F065 / C8051F067 Block ...

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C8051F060/1/2/3/4/5/6/7 Figure 5.17. ADC1L: ADC1 Data Word LSB Register.............................................. 65 Figure 5.18. ADC1 Data Word Example................................................................... 65 Figure 5.19. Calibration Coefficient Locations.......................................................... 66 Figure 5.20. Offset and Gain Register Mapping ....................................................... 67 Figure 5.21. Offset and Gain Calibration Block Diagram.......................................... ...

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Figure 7.14. ADC2LTL: ADC2 Less-Than Data Low Byte Register ......................... 98 Figure 7.15. ADC Window Compare Example: Right-Justified Single-Ended Data . 99 Figure 7.16. ADC Window Compare Example: Left-Justified Single-Ended Data.... 99 Figure 7.17. ADC Window Compare Example: Right-Justified Differential ...

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C8051F060/1/2/3/4/5/6/7 Figure 13.17. ACC: Accumulator............................................................................ 150 Figure 13.18 Register .................................................................................... 150 Figure 13.19. IE: Interrupt Enable .......................................................................... 154 Figure 13.20. IP: Interrupt Priority .......................................................................... 155 Figure 13.21. EIE1: Extended Interrupt Enable 1................................................... 156 Figure 13.22. EIE2: Extended Interrupt ...

Page 13

Figure 18.5. XBR0: Port I/O Crossbar Register 0................................................... 210 Figure 18.6. XBR1: Port I/O Crossbar Register 1................................................... 211 Figure 18.7. XBR2: Port I/O Crossbar Register 2................................................... 212 Figure 18.8. XBR3: Port I/O Crossbar Register 3................................................... 213 Figure 18.9. P0: Port0 ...

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C8051F060/1/2/3/4/5/6/7 Figure 21.1. SPI Block Diagram ............................................................................. 251 Figure 21.2. Multiple-Master Mode Connection Diagram ....................................... 254 Figure 21.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram 254 Figure 21.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection ...

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Figure 24.6. CKCON: Clock Control Register ........................................................ 293 Figure 24.7. TL0: Timer 0 Low Byte ....................................................................... 294 Figure 24.8. TL1: Timer 1 Low Byte ....................................................................... 294 Figure 24.9. TH0: Timer 0 High Byte...................................................................... 294 Figure 24.10. TH1: Timer 1 High ...

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C8051F060/1/2/3/4/5/6/7 16 Rev. 1.2 ...

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List of Tables 1. System Overview ................................................................................................... 19 Table 1.1.Product Selection Guide .......................................................................... 20 2. Absolute Maximum Ratings ................................................................................. 37 Table 2.1.Absolute Maximum Ratings* ................................................................... 37 3. Global DC Electrical Characteristics ................................................................... 38 Table 3.1.Global DC Electrical Characteristics ....................................................... 38 ...

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C8051F060/1/2/3/4/5/6/7 Table 19.1.CAN Register Index and Reset Values ............................................... 229 20. System Management BUS / I2C BUS (SMBUS0) ............................................... 235 Table 20.1.SMB0STA Status Codes and States ................................................... 248 21. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 251 Table 21.1.SPI Slave Timing ...

Page 19

System Overview The C8051F06x family of devices are fully integrated mixed-signal System-on-a-Chip MCUs with 59 digital I/O pins (C8051F060/2/4/ digital I/O pins (C8051F061/3/5/7), and two integrated 16-bit 1 Msps ADCs. Highlighted features are listed below; refer to ...

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C8051F060/1/2/3/4/5/6/7 Table 1.1. Product Selection Guide  C8051F060 4352 C8051F061 4352 -  C8051F062 4352 C8051F063 4352 -  C8051F064 4352 C8051F065 ...

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VDD VDD VDD Digital Power DGND DGND Analog Power DGND AV+ AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD Monitor WDT MONEN XTAL1 External Oscillator XTAL2 Circuit System Clock Trimmed Internal Oscillator VREF VREF ...

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C8051F060/1/2/3/4/5/6/7 VDD VDD Digital Power VDD DGND DGND Analog Power DGND AV+ AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD Monitor WDT MONEN External Oscillator XTAL1 XTAL2 Circuit System Clock Trimmed Internal Oscillator VREF ...

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VDD VDD Digital Power VDD DGND DGND Analog Power DGND AV+ AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD Monitor WDT MONEN XTAL1 External Oscillator XTAL2 Circuit System Clock Trimmed Internal Oscillator VREF VREF ...

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C8051F060/1/2/3/4/5/6/7 VDD VDD Digital Power VDD DGND DGND Analog Power DGND AV+ AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD Monitor WDT MONEN XTAL1 External Oscillator XTAL2 Circuit System Clock Trimmed Internal Oscillator VREF ...

Page 25

CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F06x family of devices utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to ...

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C8051F060/1/2/3/4/5/6/7 1.1.3. Additional Features The C8051F06x MCU family includes several key enhancements to the CIP-51 core and peripherals to improve overall performance and ease of use in end applications. The extended interrupt handler provides 22 interrupt sources into the CIP-51, ...

Page 27

On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct ...

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... MCU is halted, during single stepping breakpoint in order to keep them synchronized with instruction execution. The C8051F060DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F06x MCUs. The kit includes a Windows (95 or later) development environment, a serial adapter for connecting to the JTAG port, and a target application board with a C8051F060 MCU installed ...

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Programmable Digital I/O and Crossbar Three standard 8051 Ports (0, 1, and 2) are available on the MCUs. The C8051F060/2/4/6 have 4 addi- tional 8-bit ports ( and 7), and a 3-bit port (port 4) for a ...

Page 30

C8051F060/1/2/3/4/5/6/7 1.5. Programmable Counter Array The C8051F06x MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with 6 programmable capture/compare modules. ...

Page 31

Controller Area Network The C8051F060/1/2/3 devices feature a Controller Area Network (CAN) controller that implements serial communication using the CAN protocol. The CAN controller facilitates communication on a CAN network in accordance with the Bosch specification 2.0A (basic CAN) ...

Page 32

C8051F060/1/2/3/4/5/6/7 1.7. Serial Ports The C8051F06x MCU Family includes two Enhanced Full-Duplex UARTs, an enhanced SPI Bus, and SMBus/I2C. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very ...

Page 33

Analog to Digital Converters The C8051F060/1/2/3/4/5/6/7 devices have two on-chip 16-bit SAR ADCs (ADC0 and ADC1), which can be used independently in single-ended mode, or together in differential mode. ADC0 and ADC1 can directly access on-chip or external ...

Page 34

C8051F060/1/2/3/4/5/6/7 1.9. 10-Bit Analog to Digital Converter The C8051F060/1/2/3 devices have an on-board 10-bit SAR ADC (ADC2) with a 9-channel input multi- plexer and programmable gain amplifier. This ADC features a 200 ksps maximum throughput and true 10- bit performance ...

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Digital to Analog Converters The C8051F060/1/2/3 MCUs have two integrated 12-bit Digital to Analog Converters (DACs). The MCU data and control interface to each DAC is via the Special Function Registers. The MCU can place either or both ...

Page 36

C8051F060/1/2/3/4/5/6/7 1.11. Analog Comparators The C8051F060/1/2/3/4/5/6/7 MCUs include three analog comparators on-chip. The comparators have software programmable hysteresis and response time. Each comparator can generate an interrupt on its rising edge, falling edge, or both. The interrupts are capable of ...

Page 37

Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any pin (except VDD, AV+, AVDD, and Port 0) with respect to DGND Voltage on any Port 0 Pin with respect to ...

Page 38

C8051F060/1/2/3/4/5/6/7 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics -40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Analog Supply Voltage (AV+, (Note 1) AVDD) Digital Supply Voltage (VDD) Analog-to-Digital Supply Delta (|VDD - ...

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Pinout and Package Definitions Pin Numbers Name F060 F061 F064 F062 F063 F066 VDD 37, 64, 26, 40, 37, 64 DGND 38, 63, 27, 39, 38, 63 AV+ 11, 16, 7, 10, 11, ...

Page 40

C8051F060/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F060 F061 F064 F062 F063 F066 VRGND0 VBGAP0 VREF1 VRGND1 VBGAP1 VREF2 2 62 VREFD 3 ...

Page 41

Table 4.1. Pin Definitions (Continued) Pin Numbers Name F060 F061 F064 F062 F063 F066 P1.0/AIN2 P1.1/AIN2 P1.2/AIN2 P1.3/AIN2.3 33 ...

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C8051F060/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F060 F061 F064 F062 F063 F066 P3.4 ...

Page 43

Table 4.1. Pin Definitions (Continued) Pin Numbers Name F060 F061 F064 F062 F063 F066 P5.2/A10 86 86 P5.3/A11 85 85 P5.4/A12 84 84 P5.5/A13 83 83 P5.6/A14 82 82 P5.7/A15 81 81 P6.0/A8m P6.1/A9m ...

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C8051F060/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F060 F061 F064 F062 F063 F066 P7.2/AD2m P7.3/AD3m P7.4/AD4m P7.5/AD5m P7.6/AD6m P7.7/AD7m ...

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DAC1 1 VREF2 2 VREFD 3 VREF 4 VBGAP1 5 VREF1 6 VRGND1 7 AIN1G 8 AIN1 9 AGND 10 AV+ 11 CNVSTR1 12 AVDD 13 AGND 14 CNVSTR0 15 AV+ 16 AGND 17 AIN0 18 AIN0G 19 VRGND0 20 ...

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C8051F060/1/2/3/4/5/6 VREF 4 VBGAP1 5 VREF1 6 VRGND1 7 AIN1G 8 AIN1 9 AGND 10 AV+ 11 CNVSTR1 12 AVDD 13 AGND 14 CNVSTR0 15 AV+ 16 AGND 17 AIN0 18 AIN0G 19 VRGND0 ...

Page 47

PIN 1 DESIGNATOR Figure 4.3. TQFP-100 Package Drawing C8051F060/1/2/3/4/5/6 Rev. 1.2 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 ...

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C8051F060/1/2/3/4/5/6/7 VBGAP1 1 VREF1 2 VRGND1 3 AIN1G 4 AIN1 5 AGND 6 AV+ 7 CNVSTR1 8 CNVSTR0 9 AV+ 10 AGND 11 AIN0 12 AIN0G 13 VRGND0 14 VREF0 15 VBGAP0 16 Figure 4.4. C8051F061 / C8051F063 Pinout Diagram ...

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VBGAP1 1 VREF1 2 VRGND1 3 AIN1G 4 AIN1 5 AGND 6 AV+ 7 CNVSTR1 8 C8051F065/067 CNVSTR0 9 AV+ 10 AGND 11 AIN0 12 AIN0G 13 VRGND0 14 VREF0 15 VBGAP0 16 Figure 4.5. C8051F065 / C8051F067 Pinout Diagram ...

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C8051F060/1/2/3/4/5/6 PIN 1 DESIGNATOR Figure 4.6. TQFP-64 Package Drawing Rev. 1.2 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 ...

Page 51

ADCs (ADC0 and ADC1) The ADC subsystem for the C8051F060/1/2/3/4/5/6/7 consists of two 1 Msps, 16-bit successive-approxi- mation-register ADCs with integrated track-and-hold, a Programmable Window Detector, and a DMA inter- face (see block diagrams in Figure 5.1 and ...

Page 52

C8051F060/1/2/3/4/5/6/7 16-Bit AIN0 SAR ADC0 AIN0G 16-Bit AIN1 SAR ADC1 AIN1G ADC1H DMA Interface ADC0GTH Figure 5.2. 16-bit ADC0 and ADC1 Data Path Diagram 5.1. Single-Ended or Differential Operation ADC0 and ADC1 can be programmed to operate independently as single-ended ...

Page 53

Voltage Reference The voltage reference circuitries for ADC0 and ADC1 allow for many different voltage reference configura- tions. Each ADC has the capability to use its own dedicated, on-chip voltage reference off-chip refer- ence circuit. A block ...

Page 54

C8051F060/1/2/3/4/5/6/7 5.3. ADC Modes of Operation ADC0 and ADC1 have a maximum conversion speed of 1 Msps. The conversion clocks for the ADCs are derived from the system clock. The ADCnSC bits in the ADCnCF register determine how many system ...

Page 55

A. ADC Timing for External Trigger Source CNVSTRn Track B. ADC Timing for Internal Trigger Sources Timer 2, Timer 3 Overflow; Write '1' to ADnBUSY ADCnTM=1 Track ADCnTM=0 Track Figure 5.4. ADC Track and Conversion Example Timing Table 5.1. Conversion ...

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C8051F060/1/2/3/4/5/6/7 5.3.3. Settling Time Requirements The ADC requires a minimum tracking time before an accurate conversion can be performed. This tracking time is determined by the ADC input resistance, the ADC sampling capacitance, any external source resis- tance, and the ...

Page 57

Figure 5.6. AMX0SL: AMUX Configuration Register R/W R/W R/W - DIFFSEL - Bit7 Bit6 Bit5 Bit 7: RESERVED. Write to 0b. Bit 6: DIFFSEL: Fully Differential Conversion Mode Select Bit. 0: Operate In Single-Ended Mode. 1: Operate In Differential Mode. ...

Page 58

C8051F060/1/2/3/4/5/6/7 Figure 5.7. ADC0CF: ADC0 Configuration Register R/W R/W R/W AD0SC3 AD0SC2 AD0SC1 Bit7 Bit6 Bit5 Bits 7-4: AD0SC3-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is divided down from the system clock according to the AD0SC bits ...

Page 59

Figure 5.8. ADC1CF: ADC1 Configuration Register R/W R/W R/W AD1SC3 AD1SC2 AD1SC1 Bit7 Bit6 Bit5 Bits 7-4: AD1SC3-0: ADC1 SAR Conversion Clock Period Bits. SAR Conversion clock is divided down from the system clock according to the AD1SC bits (AD1SC3-0). ...

Page 60

C8051F060/1/2/3/4/5/6/7 Figure 5.9. ADC0CN: ADC0 Control Register R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY Bit7 Bit6 Bit5 Bit 7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for ...

Page 61

Figure 5.10. ADC1CN: ADC1 Control Register R/W R/W R/W AD1EN AD1TM AD1INT AD1BUSY Bit7 Bit6 Bit5 Bit 7: AD1EN: ADC1 Enable Bit. 0: ADC1 Disabled. ADC1 is in low-power shutdown. 1: ADC1 Enabled. ADC1 is active and ready for data ...

Page 62

C8051F060/1/2/3/4/5/6/7 Figure 5.11. REF0CN: Reference Control Register 0 R/W R/W R Bit7 Bit6 Bit5 Bits7-2: RESERVED. Read = 000000b; Write = 000000b. Bit1: BIASE0: ADC0 Bias Generator Enable Bit. (Must be ‘1’ if using ADC0). 0: ADC0 ...

Page 63

Figure 5.13. ADC0H: ADC0 Data Word MSB Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: ADC0 Data Word High-Order Bits. Figure 5.14. ADC0L: ADC0 Data Word LSB Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: ADC0 Data Word ...

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C8051F060/1/2/3/4/5/6/7 Figure 5.15. ADC0 Data Word Example 16-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows: Example: ADC0 Data Word Conversion Map, AIN0 Input in Single-Ended Mode (AMX0SL = 0x00) AIN0-AIN0G (Volts) VREF * (65535/65536) VREF ...

Page 65

Figure 5.16. ADC1H: ADC1 Data Word MSB Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: ADC1 Data Word High-Order Bits. Figure 5.17. ADC1L: ADC1 Data Word LSB Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: ADC1 Data Word ...

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C8051F060/1/2/3/4/5/6/7 5.4. Calibration The ADCs are calibrated for linearity, offset, and gain in production. ADC0 and ADC1 can also be indepen- dently calibrated for each of these parameters in-system. Calibrations are initiated using bits in the ADC0 or ADC1 Configuration ...

Page 67

Figure 5.20. Offset and Gain Register Mapping The offset register value affects the offset at the analog input as follows: Offset Register (14 Bits) Approximate Offset Change (V) 0x3FFF 0x2000 0x0000 0x2000 Offset Register  ----------------------------------------------------------- - Offset Change The ...

Page 68

C8051F060/1/2/3/4/5/6/7 Figure 5.22. ADC0CPT: ADC Calibration Pointer Register R/W R/W R/W INCR ADCSEL CPTR5 Bit7 Bit6 Bit5 Bit 7: INCR: Pointer Address Automatic Increment. 0: Disable Auto-Increment. 1: Enable Auto-Increment. CPTR5-0 will automatically be incremented after each read or write ...

Page 69

ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and ...

Page 70

C8051F060/1/2/3/4/5/6/7 Figure 5.26. ADC0LTH: ADC0 Less-Than Data High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: High byte of ADC0 Less-Than Data Word. Figure 5.27. ADC0LTL: ADC0 Less-Than Data Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 ...

Page 71

Figure 5.28. 16-Bit ADC0 Window Interrupt Example: Single-Ended Data Input Voltage ADC0 Data (AIN0 - AIN0G) Word REF x (65535/65536) 0xFFFF AD0WINT not affected 0x2001 REF x (8192/65536) 0x2000 ADC0LTH:ADC0LTL 0x1FFF AD0WINT=1 0x1001 REF x (4096/65536) 0x1000 ADC0GTH:ADC0GTL 0x0FFF AD0WINT ...

Page 72

C8051F060/1/2/3/4/5/6/7 Figure 5.29. 16-Bit ADC0 Window Interrupt Example: Differential Data Input Voltage ADC0 Data (AIN0 - AIN1) Word REF x (32767/32768) 0x7FFF AD0WINT not affected 0x1001 REF x (4096/32768) 0x1000 ADC0LTH:ADC0LTL 0x0FFF AD0WINT=1 0x0000 REF x (-1/32768) 0xFFFF ADC0GTH:ADC0GTL 0xFFFE ...

Page 73

Table 5.2. 16-Bit ADC0 and ADC1 Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, VREF = 2.50 V (REFBE=0), -40 to +85 °C unless otherwise specified Parameter Conditions DC Accuracy Resolution Integral Nonlinearity Single-Ended ...

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C8051F060/1/2/3/4/5/6/7 Table 5.2. 16-Bit ADC0 and ADC1 Electrical Characteristics (Continued) VDD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, VREF = 2.50 V (REFBE=0), -40 to +85 °C unless otherwise specified Parameter Conditions Operating Input Range AIN0 ...

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Direct Memory Access Interface (DMA0) The DMA interface works in conjunction with ADC0 and ADC1 to write ADC outputs directly to a specified region of XRAM. The DMA interface is configured by software using the Special Function Registers shown ...

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C8051F060/1/2/3/4/5/6/7 6.2. DMA0 Instruction Format DMA instructions can request single-ended data from both ADC0 and ADC1, as well as the differential combination of the two ADC inputs. The instruction format is identical to the DMA0IDT register, shown in Figure 6.7. ...

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Pointer Registers are initialized to the values contained in the DMA Data Address Beginning Registers (DMA0DAH and DMA0DAL). The Data Address Pointer Registers are automatically incremented after each data write by the DMA interface. 6.4. Instruction ...

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C8051F060/1/2/3/4/5/6/7 6.5. Instruction Execution in Mode 1 When the DMA interface begins an operation cycle, the DMA Instruction Status Register (DMA0ISW, Figure 6.9) is loaded with the address contained within the DMA Instruction Boundary Register (DMA0BND, Figure 6.8). The instruction ...

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Interrupt Sources The DMA contains multiple interrupt sources. Some of these can be individually enabled to generate inter- rupts as necessary. The DMA Control Register (DMA0CN, Figure 6.4) and DMA Configuration Register (DMA0CF, Figure 6.5) contain the enable bits ...

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C8051F060/1/2/3/4/5/6/7 Figure 6.4. DMA0CN: DMA0 Control Register 3 SFR Page: 0xD8 (bit addressable) SFR Address: R/W R/W R/W DMA0EN DMA0INT DMA0MD DMA0DE1 DMA0DE0 DMA0DOE DMA0DO1 DMA0DO0 00000000 Bit7 Bit6 Bit5 Bit 7: DMA0EN: DMA0 Enable. Write: 0: Stop DMA0 Operations. ...

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Figure 6.5. DMA0CF: DMA0 Configuration Register 3 SFR Page: 0xF8 (bit addressable) SFR Address: R/W R R/W DMA0HLT DMA0XBY - Bit7 Bit6 Bit5 Bit 7: DMA0HLT: Halt DMA0 Off-Chip XRAM Access (C8051F060/2/4/6 Only). 0: DMA0 has complete access to off-chip ...

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C8051F060/1/2/3/4/5/6/7 Figure 6.6. DMA0IPT: DMA0 Instruction Write Address Register 3 SFR Page: 0xDD SFR Address R Bit7 Bit6 Bit5 Bits 7-6: Unused. Bits 5-0: DMA0 instruction address to write (or read). When DMA0IDT is written or ...

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Figure 6.8. DMA0BND: DMA0 Instruction Boundary Register 3 SFR Page: 0xFD SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits 7-6: Unused. Bits 5-0: DMA0 instruction address to begin with when executing DMA instructions. Figure 6.9. DMA0ISW: DMA0 ...

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C8051F060/1/2/3/4/5/6/7 Figure 6.10. DMA0DAH: DMA0 Data Address Beginning MSB Register 3 SFR Page: 0xDA SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: DMA0 Address Beginning High-Order Bits. Figure 6.11. DMA0DAL: DMA0 Data Address Beginning LSB Register 3 SFR ...

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Figure 6.14. DMA0CTH: DMA0 Repeat Counter Limit MSB Register 3 SFR Page: 0xFA SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: DMA0 Repeat Counter Limit High-Order Bits. Figure 6.15. DMA0CTL: DMA0 Repeat Counter Limit LSB Register 3 SFR ...

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C8051F060/1/2/3/4/5/6/7 86 Rev. 1.2 ...

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ADC (ADC2, C8051F060/1/2/3) The ADC2 subsystem for the C8051F060/1/2/3 consists of an analog multiplexer (referred to as AMUX2), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and pro- grammable window detector (see block diagram in Figure ...

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C8051F060/1/2/3/4/5/6/7 7.1. Analog Multiplexer The analog multiplexer (AMUX2) selects the inputs to the ADC, allowing any of the pins on Port measured in single-ended mode differential pair. Additionally, the on-chip temperature sensor may be ...

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Figure 7.2. Temperature Sensor Transfer Function -50 7.2. Modes of Operation ADC2 has a maximum conversion speed of 200 ksps. The ADC2 conversion clock is a divided version of the system clock, determined by the AD2SC bits in the ADC2CF ...

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C8051F060/1/2/3/4/5/6/7 7.2.2. Tracking Modes The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode. In its default state, the ADC2 input is continuously tracked, except when a conversion is in progress. When the AD2TM bit is logic 1, ADC2 ...

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Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX2 resistance, the ADC2 sampling capacitance, any external source resistance, and the accuracy required for the ...

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C8051F060/1/2/3/4/5/6/7 Figure 7.5. AMX2CF: AMUX2 Configuration Register 2 SFR Page: 0xBA SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits 7-4: UNUSED. Read = 0000b; Write = don’t care. Bit 3: AIN67IC: AIN2.6, AIN2.7 Input Pair Configuration ...

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Figure 7.6. AMX2SL: AMUX2 Channel Select Register 2 SFR Page: 0xBB SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits 7-4: UNUSED. Read = 0000b; Write = don’t care. Bits 3-0: AMX2AD3-0: AMX2 Address Bits. 0000-1111b: ADC ...

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C8051F060/1/2/3/4/5/6/7 Figure 7.7. ADC2CF: ADC2 Configuration Register 2 SFR Page: 0xBC SFR Address: R/W R/W R/W AD2SC4 AD2SC3 AD2SC2 Bit7 Bit6 Bit5 Bits7-3: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the ...

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Figure 7.8. ADC2H: ADC2 Data Word MSB Register 2 SFR Page: 0xBF SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC2 Data Word High-Order Bits. For AD2LJST = 0: Bits 7-2 are the sign extension of Bit 1. Bits ...

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C8051F060/1/2/3/4/5/6/7 Figure 7.10. ADC2CN: ADC2 Control Register 2 SFR Page: 0xE8 (bit addressable) SFR Address: R/W R/W R/W AD2EN AD2TM AD2INT Bit7 Bit6 Bit5 Bit 7: AD2EN: ADC2 Enable Bit. 0: ADC2 Disabled. ADC2 is in low-power shutdown. 1: ADC2 ...

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Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC2 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...

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C8051F060/1/2/3/4/5/6/7 Figure 7.13. ADC2LTH: ADC2 Less-Than Data High Byte Register 2 SFR Page: 0xC7 SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: High byte of ADC2 Less-Than Data Word. Figure 7.14. ADC2LTL: ADC2 Less-Than Data Low Byte Register 2 ...

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Window Detector In Single-Ended Mode Figure 7.15 shows two example window comparisons for right-justified, single-ended data, with ADC2LTH:ADC2LTL = 0x0080 (128d) and ADC2GTH:ADC2GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF * ...

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C8051F060/1/2/3/4/5/6/7 7.3.2. Window Detector In Differential Mode Figure 7.17 shows two example window comparisons for right-justified, differential data, with ADC2LTH:ADC2LTL = 0x0040 (+64d) and ADC2GTH:ADC2GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between ...

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Table 7.1. ADC2 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V (REFSL=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified Parameter Conditions DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error ...

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C8051F060/1/2/3/4/5/6/7 102 Rev. 1.2 ...

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DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) The C8051F060/1/2/3 devices include two on-chip 12-bit voltage-mode Digital-to-Analog Converters (DACs). Each DAC has an output swing (VREF-1LSB) for a corresponding input code range of 0x000 to ...

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C8051F060/1/2/3/4/5/6/7 8.1. DAC Output Scheduling Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. The following examples are written in terms of DAC0, but DAC1 operation is identical. ...

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Figure 8.2. DAC0H: DAC0 High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Most Significant Byte. Figure 8.3. DAC0L: DAC0 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Least Significant Byte. ...

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C8051F060/1/2/3/4/5/6/7 Figure 8.4. DAC0CN: DAC0 Control Register R/W R/W R/W DAC0EN - - Bit7 Bit6 Bit5 Bit7: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. 1: DAC0 Enabled. DAC0 Output ...

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Figure 8.5. DAC1H: DAC1 High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Most Significant Byte. Figure 8.6. DAC1L: DAC1 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Least Significant Byte. ...

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C8051F060/1/2/3/4/5/6/7 Figure 8.7. DAC1CN: DAC1 Control Register R/W R/W R/W DAC1EN - - Bit7 Bit6 Bit5 Bit7: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. 1: DAC1 Enabled. DAC1 Output ...

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Table 8.1. DAC Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), No Output Load unless otherwise specified Parameter Conditions Static Performance Resolution Integral Nonlinearity Differential Nonlinearity Output Noise No Output ...

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C8051F060/1/2/3/4/5/6/7 110 Rev. 1.2 ...

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Voltage Reference 2 (C8051F060/2) The voltage reference circuitry offers full flexibility in operating the ADC2 and DAC modules. Two voltage reference input pins allow ADC2 and the two DACs to reference an external voltage reference or the on- chip ...

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C8051F060/1/2/3/4/5/6/7 The temperature sensor connects to the highest order input of the ADC2 input multiplexer (see “7. 10-Bit ADC (ADC2, C8051F060/1/2/3)” on page ables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state, and any ...

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Voltage Reference 2 (C8051F061/3) The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system ...

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C8051F060/1/2/3/4/5/6/7 The temperature sensor connects to the highest order input of the ADC2 input multiplexer (see “7. 10-Bit ADC (ADC2, C8051F060/1/2/3)” on page ables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state, and any ...

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Voltage Reference 2 (C8051F064/5/6/7) The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed to the VREF pin as shown in ...

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C8051F060/1/2/3/4/5/6/7 Figure 11.2. REF2CN: Reference Control Register 2 R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bits2-3: RESERVED. Must Write to 00b. Bit1: BIASE: ADC/DAC Bias Generator Enable Bit. (Must ...

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Comparators C8051F06x family of devices include three on-chip programmable voltage comparators, shown in Figure 12.1. Each comparator offers programmable response time and hysteresis. When assigned to a Port pin, the Comparator output may be configured as open drain or ...

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C8051F060/1/2/3/4/5/6/7 Comparator inputs can be externally driven from -0. (VDD) + 0.25 V without damage or upset. The complete electrical specifications for the Comparator are given in Table 12.1. The Comparator response time may be configured in software ...

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Comparator interrupts can be generated on either rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see falling -edge interrupts are enabled using the comparator’s Rising/Falling Edge Interrupt Enable Bits (CPn- RIE and CPnFIE) in their respective Comparator ...

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C8051F060/1/2/3/4/5/6/7 Figure 12.3. CPTnCN: Comparator 0, 1, and 2 Control Register R/W R/W R/W CPnEN CPnOUT CPnRIF Bit7 Bit6 Bit5 SFR Address: CPT0CN: 0x88; CPT1CN: 0x88; CPT2CN: 0x88 SFR Pages: CPT0CN: page 1; CPT1CN: page 2; CPT2CN: page 3 Bit7: ...

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Figure 12.4. CPTnMD: Comparator Mode Selection Register R/W R/W R CPnRIE Bit7 Bit6 Bit5 SFR Address: CPT0MD: 0x89; CPT1MD: 0x89; CPT2MD: 0x89 SFR Page: CPT0MD: page 1; CPT1MD: page 2; CPT2MD: page 3 Bits7-6: UNUSED. Read = 00b, ...

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C8051F060/1/2/3/4/5/6/7 Table 12.1. Comparator Electrical Characteristics VDD = 3.0 V, -40 to +85 °C unless otherwise specified. Parameter Conditions Response Time, CPn+ - CPn- = 100 mV Mode 0 CPn+ - CPn Response Time, CPn+ - CPn- ...

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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...

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C8051F060/1/2/3/4/5/6/7 The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 13.1 for a block diagram). The CIP-51 includes the following features: Performance The CIP-51 ...

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Programming and Debugging Support A JTAG-based serial interface is provided for in-system programming of the Flash program memory and communication with on-chip debug support logic. The re-programmable Flash can also be read and changed a single byte at a time ...

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C8051F060/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary Mnemonic Description ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC ...

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Table 13.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate ...

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C8051F060/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement of direct bit to Carry MOV C, ...

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Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte ...

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C8051F060/1/2/3/4/5/6/7 13.2. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...

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Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. Either ...

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C8051F060/1/2/3/4/5/6/7 and each CALL pushes two record bits onto the register. (A POP or decrement SP pops one record bit, and a RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on ...

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Interrupt Logic CIP-51 Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFRPGCN). This function defaults to ‘enabled’ ...

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C8051F060/1/2/3/4/5/6/7 13.2.6.3.SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and ...

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While CIP-51 executes in-line code (writing values to Port 5 in this example), ADC2 Window Comparator Interrupt occurs. The CIP-51 vectors to the ADC2 Window Comparator ISR and pushes the current SFR Page value (SFR Page 0x0F) into SFRNEXT in ...

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C8051F060/1/2/3/4/5/6/7 While in the ADC2 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the ADC2 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the ...

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On exit from the PCA interrupt service routine, the CIP-51 will return to the ADC2 Window Comparator ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be auto- matically popped off of ...

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C8051F060/1/2/3/4/5/6/7 On the execution of the RETI instruction in the ADC2 Window Comparator ISR, the value in SFRPAGE register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the Port 5 SFR bits as it did prior ...

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Figure 13.9. SFRPGCN: SFR Page Control Register R/W R/W R Bit7 Bit6 Bit5 Bits7-1: Reserved. Bit0: SFRPGEN: SFR Automatic Page Control Enable. Upon interrupt, the C8051 Core will vector to the specified interrupt service routine and automatically ...

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C8051F060/1/2/3/4/5/6/7 Figure 13.11. SFRNEXT: SFR Next Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT ...

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Table 13.2. Special Function Register (SFR) Memory Map A SFR 0(8) 1( SPI0CN PCA0L PCA0H 0 1 CAN0CN DMA0CF DMA0CTL DMA0CTH ...

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C8051F060/1/2/3/4/5/6/7 Table 13.2. Special Function Register (SFR) Memory Map (ALL PAGES SADDR0 (ALL PAGES EMI0TC EMI0CN (ALL PAGES SCON0 ...

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Table 13.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description B 0xF0 All Pages B Register ACC 0xE0 All Pages Accumulator ADC0CCF 0xBB ADC0CF 0xBC ADC0CN 0xE8 ADC0CPT ...

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C8051F060/1/2/3/4/5/6/7 Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description CPT2MD 0x89 DAC0CN 0xD4 DAC0H 0xD3 DAC0L 0xD2 DAC1CN 0xD4 DAC1H 0xD3 DAC1L 0xD2 DMA0BND 0xFD ...

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Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description P2MDIN 0xAE P2MDOUT 0xA6 P3 0xB0 All Pages Port 3 Latch P3MDOUT 0xA7 P4 0xC8 P4MDOUT 0x9C ...

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C8051F060/1/2/3/4/5/6/7 Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description REF0CN 0xD1 REF1CN 0xD1 REF2CN 0xD1 RSTSRC 0xEF SADDR0 0xA9 SADEN0 0xB9 SBUF0 0x99 SBUF1 0x99 ...

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Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description TMR4L 0xCC WDTCN 0xFF All Pages Watchdog Timer Control XBR0 0xE1 XBR1 0xE2 XBR2 0xE3 XBR3 0xE4 ...

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C8051F060/1/2/3/4/5/6/7 13.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which ...

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Figure 13.16. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared ...

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C8051F060/1/2/3/4/5/6/7 Figure 13.17. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register ...

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Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version ...

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C8051F060/1/2/3/4/5/6/7 Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 0x002B Serial Peripheral Interface 0x0033 SMBus Interface 0x003B ADC0 Window 0x0043 ...

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Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be ...

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C8051F060/1/2/3/4/5/6/7 13.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the ...

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Figure 13.20. IP: Interrupt Priority R/W R/W R PT2 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. ...

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C8051F060/1/2/3/4/5/6/7 Figure 13.21. EIE1: Extended Interrupt Enable 1 R/W R/W R/W EADC0 CP2IE CP1IE Bit7 Bit6 Bit5 Bit7: EADC0: Enable ADC0 End of Conversion Interrupt. This bit sets the masking of the ADC0 End of Conversion Interrupt. 0: Disable ADC0 ...

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Figure 13.22. EIE2: Extended Interrupt Enable 2 R/W R/W R/W EDMA0 ES1 ECAN0 Bit7 Bit6 Bit5 Bit7: EDMA0: Enable DMA0 Interrupt. This bit sets the masking of the DMA0 Interrupt. 0: Disable DMA0 interrupt. 1: Enable DMA0 interrupt. Bit6: ES1: ...

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C8051F060/1/2/3/4/5/6/7 Figure 13.23. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PADC0 PCP2 PCP1 Bit7 Bit6 Bit5 Bit7: PADC0: ADC End of Conversion Interrupt Priority Control. This bit sets the priority of the ADC0 End of Conversion Interrupt. 0: ADC0 ...

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Figure 13.24. EIP2: Extended Interrupt Priority 2 R/W R/W R/W PDMA0 PS1 PCAN0 Bit7 Bit6 Bit5 Bit7: PDMA0: DMA0 Interrupt Priority Control. This bit sets the priority of the DMA0 interrupt. 0: DMA0 interrupt set to low priority. 1: DMA0 ...

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C8051F060/1/2/3/4/5/6/7 13.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all ...

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Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes. In Stop mode, the CPU and internal oscillators are stopped, effectively shutting ...

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C8051F060/1/2/3/4/5/6/7 162 Rev. 1.2 ...

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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...

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C8051F060/1/2/3/4/5/6/7 14.1. Power-on Reset The C8051F060/1/2/3/4/5/6/7 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the V RST to Table 14.1 for the Electrical Characteristics of the power supply monitor circuit. ...

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The PINRSF flag (RST- SRC.0) is set on exit from an external reset. 14.4. Missing Clock Detector Reset The Missing Clock Detector is essentially a one-shot ...

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C8051F060/1/2/3/4/5/6/7 14.7.1. Enable/Reset WDT The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica- tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. ...

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For a 3 MHz system clock, this provides an interval range of 0.021 ms to 349.5 ms. WDTCN.7 must be logic 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads 111b after a system reset. Figure ...

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C8051F060/1/2/3/4/5/6/7 Figure 14.4. RSTSRC: Reset Source Register R R/W R/W - CNVRSEF C0RSEF Bit7 Bit6 Bit5 Bit7: Reserved. Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag Write: 0: CNVSTR2 is not a reset source. 1: CNVSTR2 is a reset ...

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Table 14.1. Reset Electrical Characteristics -40 to +85 °C unless otherwise specified. Parameter I /RST Output Low Voltage OL /RST Input High Voltage /RST Input Low Voltage /RST Input Leakage Current /RST = 0.0 V VDD for /RST Output Valid ...

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C8051F060/1/2/3/4/5/6/7 170 Rev. 1.2 ...

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Oscillators C8051F060/1/2/3/4/5/6/7 devices include a programmable internal oscillator and an external oscillator drive circuit. The internal oscillator can be enabled, disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 15.1. The system clock can be ...

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C8051F060/1/2/3/4/5/6/7 . Figure 15.2. OSCICL: Internal Oscillator Calibration Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: OSCICL: Internal Oscillator Calibration Register This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. ...

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Table 15.1. Internal Oscillator Electrical Characteristics -40°C to +85°C unles otherwise specified. Parameter Calibrated Internal Oscillator Frequency Internal Oscillator Supply OSCICN Current (3.0V Supply) 15.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ...

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C8051F060/1/2/3/4/5/6/7 Figure 15.5. OSCXCN: External Oscillator Control Register R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Valid only when XOSCMD = 11x.). 0: Crystal Oscillator is unused or not yet stable. 1: ...

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External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 15.1, Option 1. The External Oscillator Frequency Control value (XFCN) should ...

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C8051F060/1/2/3/4/5/6/7 176 Rev. 1.2 ...

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Flash Memory The C8051F060/1/2/3/4/5/6/7 devices include on-chip, reprogrammable Flash memory for program code and non-volatile data storage. The C8051F060/1/2/3/4/5 include 128 bytes of Flash, and the C8051F066/7 include 128 bytes of Flash. The ...

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C8051F060/1/2/3/4/5/6/7 Step 8. Clear the PSWE bit to redirect MOVX write commands to the XRAM data space. Step 9. Re-enable interrupts. Write/Erase timing is automatically controlled by hardware. Note that code execution in the 8051 is stalled while the Flash ...

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Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as prevent the viewing of proprietary program code and constants. The Program Store Write Enable (PSCTL.0) and the Program ...

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C8051F060/1/2/3/4/5/6/7 Figure 16.1. C8051F060/1/2/3/4/5 Flash Program Memory Map and Security Bytes Read and Write/Erase Security Bits (Bit 7 is MSB) Bit Memory Block 7 0xE000 - 0xFBFD 6 0xC000 - 0xDFFF 5 0xA000 - 0xBFFF 4 0x8000 - 0x9FFF 3 ...

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Figure 16.2. C8051F066/7 Flash Program Memory Map and Security Bytes Read and Write/Erase Security Bits (Bit 7 is MSB) Bit Memory Block 7 N/A 6 N/A 5 N/A 4 N/A 3 0x6000 - 0x7FFD 2 0x4000 - 0x5FFF 1 0x2000 ...

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C8051F060/1/2/3/4/5/6/7 ing at 0x0000 up to (but excluding) the FAL address. Software in the upper partition can execute code in the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruc- tion. (Executing a ...

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Summary of Flash Security Options There are three Flash access methods supported on the C8051F060/1/2/3/4/5/6/7; 1) Accessing Flash through the JTAG debug interface, 2) Accessing Flash from firmware residing below the Flash Access Limit, and 3) Accessing Flash from ...

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C8051F060/1/2/3/4/5/6/7 Figure 16.4. FLSCL: Flash Memory Control R/W R/W R/W FOSE FRAE Reserved Bit7 Bit6 Bit5 Bit 7: FOSE: Flash One-Shot Timer Enable This is the timer that turns off the sense amps after a Flash read. 0: Flash One-Shot ...

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Figure 16.5. PSCTL: Program Store Read/Write Control R/W R/W R Bit7 Bit6 Bit5 Bits 7-3: UNUSED. Read = 00000b, Write = don't care. Bit 2: SFLE: Scratchpad Flash Memory Access Enable When this bit is set, Flash ...

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C8051F060/1/2/3/4/5/6/7 186 Rev. 1.2 ...

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External Data Memory Interface and On-Chip XRAM The C8051F060/1/2/3/4/5/6/7 MCUs include 4 k bytes of on-chip RAM mapped into the external data memory space (XRAM). In addition, the C8051F060/2/4/6 include an External Data Memory Interface which can be used ...

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C8051F060/1/2/3/4/5/6/7 17.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of four steps: 1. Enable the EMIF on the High Ports (P7, P6, P5, and P4). 2. Configure the Output Modes of the port pins as either ...

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Figure 17.1. EMI0CN: External Memory Interface Control R/W R/W R/W PGSEL7 PGSEL6 PGSEL5 Bit7 Bit6 Bit5 Bits7-0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using ...

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C8051F060/1/2/3/4/5/6/7 17.4. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 17.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus ...

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Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non- multiplexed Configuration is shown in Figure 17.4. See page 196 for more information about Non-multiplexed operation. Figure 17.4. ...

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C8051F060/1/2/3/4/5/6/7 17.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 17.5, based on the EMIF Mode bits in the EMI0CF register (Figure 17.2). These modes are summarized below. More ...

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Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off- chip space. • Effective addresses below the 4 kB boundary will access on-chip XRAM space. ...

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C8051F060/1/2/3/4/5/6/7 17.6. Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements. The Address Setup time, Address Hold time and /WR strobe widths, and ...

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Table 17.1 lists the AC parameters for the External Memory Interface, and Figure 17.7 through Figure 17.12 show the timing diagrams for the different External Memory Interface modes and MOVX operations. C8051F060/1/2/3/4/5/6/7 Rev. 1.2 195 ...

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C8051F060/1/2/3/4/5/6/7 17.6.1. Non-multiplexed Mode 17.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. Figure 17.7. Non-multiplexed 16-bit MOVX Timing ADDR[15:8] P5 ADDR[7:0] P6 DATA[7:0] P7 /WR P4.7 /RD P4.6 ADDR[15:8] P5 ADDR[7:0] P6 DATA[7:0] P7 /RD P4.6 /WR P4.7 196 Nonmuxed ...

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MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Figure 17.8. Non-multiplexed 8-bit MOVX without Bank Select Timing ADDR[15:8] ADDR[7:0] P6 DATA[7:0] P7 /WR P4.7 /RD P4.6 ADDR[15:8] ADDR[7:0] P6 DATA[7:0] P7 /RD P4.6 /WR P4.7 C8051F060/1/2/3/4/5/6/7 Nonmuxed 8-bit ...

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C8051F060/1/2/3/4/5/6/7 17.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. Figure 17.9. Non-multiplexed 8-bit MOVX with Bank Select Timing ADDR[15:8] P5 ADDR[7:0] P6 DATA[7:0] P7 /WR P4.7 /RD P4.6 ADDR[15:8] P5 ADDR[7:0] P6 DATA[7:0] P7 /RD P4.6 /WR P4.7 198 Nonmuxed ...

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Multiplexed Mode 17.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. Figure 17.10. Multiplexed 16-bit MOVX Timing ADDR[15:8] P6 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P4.5 /WR P4.7 /RD P4.6 ADDR[15:8] P6 EMIF ADDRESS (8 LSBs) ...

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C8051F060/1/2/3/4/5/6/7 17.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. Figure 17.11. Multiplexed 8-bit MOVX without Bank Select Timing ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P4.5 /WR P4.7 /RD P4.6 ADDR[15:8] ...

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