C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 177

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

16.
The C8051F060/1/2/3/4/5/6/7 devices include on-chip, reprogrammable Flash memory for program code
and non-volatile data storage. The C8051F060/1/2/3/4/5 include 64 k + 128 bytes of Flash, and the
C8051F066/7 include 32 k + 128 bytes of Flash. The Flash memory can be programmed in-system, a sin-
gle byte at a time, through the JTAG interface or by software using the MOVX write instructions. Once
cleared to logic 0, a Flash bit must be erased to set it back to logic 1. The bytes would typically be erased
(set to 0xFF) before being reprogrammed. Flash write and erase operations are automatically timed by
hardware for proper execution; data polling to determine the end of the write/erase operation is not
required. The CPU is stalled during write/erase operations while the device peripherals remain active.
Interrupts that occur during Flash write/erase operations are held, and are then serviced in their priority
order once the Flash operation has completed. Refer to Table 16.1 for the electrical characteristics of the
Flash memory.
16.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the JTAG interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial-
ized device. For details on the JTAG commands to program Flash memory, see
1149.1)” on page
The Flash memory can be programmed from software using the MOVX write instruction with the address
and data byte to be programmed provided as normal operands. Before writing to Flash memory using
MOVX, Flash write operations must be enabled by setting the PSWE Program Store Write Enable bit
(PSCTL.0) to logic 1. This directs the MOVX writes to Flash memory instead of to XRAM, which is the
default target. The PSWE bit remains set until cleared by software. To avoid errant Flash writes, it is rec-
ommended that interrupts be disabled while the PSWE bit is logic 1.
Flash memory is read using the MOVC instruction. MOVX reads are always directed to XRAM, regardless
of the state of PSWE.
NOTE: To ensure the integrity of Flash memory contents, it is strongly recommended that the on-
chip VDD monitor be enabled by connecting the VDD monitor enable pin (MONEN) to VDD and set-
ting the PORSF bit in the RSTSRC register to ‘1’ in any system that writes and/or erases Flash
memory from software. See “Reset Sources” on page 163 for more information.
A write to Flash memory can clear bits but cannot set them; only an erase operation can set bits in Flash.
A byte location to be programmed must be erased before a new value can be written. The Flash
memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in
the page to 0xFF). The following steps illustrate the algorithm for programming Flash from user software.
Flash Memory
Step 1. Disable interrupts.
Step 2. Set FLWE (FLSCL.0) to enable Flash writes/erases via user software.
Step 3. Set PSEE (PSCTL.1) to enable Flash erases.
Step 4. Set PSWE (PSCTL.0) to redirect MOVX commands to write to Flash.
Step 5. Use the MOVX command to write a data byte to any location within the 512-byte page to
Step 6. Clear PSEE to disable Flash erases
Step 7. Use the MOVX command to write a data byte to the desired byte location within the
be erased.
erased 512-byte page. Repeat this step until all desired bytes are written (within the target
page).
317.
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Section “26. JTAG (IEEE
177