C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 296

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
24.2.2. Capture Mode
In Capture Mode, Timer 2, 3, and 4 will operate as a 16-bit counter/timer with capture facility. When the
Timer External Enable bit (found in the TMRnCN register) is set to ‘1’, a high-to-low transition on the TnEX
input pin causes the 16-bit value in the associated timer (THn, TLn) to be loaded into the capture registers
(RCAPnH, RCAPnL). If a capture is triggered in the counter/timer, the Timer External Flag (TMRnCN.6)
will be set to ‘1’ and an interrupt will occur if the interrupt is enabled. See
on page 151
As the 16-bit timer register increments and overflows TMRnH:TMRnL, the TFn Timer Overflow/Underflow
Flag (TMRnCN.7) is set to ‘1’ and an interrupt will occur if the interrupt is enabled. The timer can be config-
ured to count down by setting the Decrement Enable Bit (TMRnCF.0) to ‘1’. This will cause the timer to
decrement with every timer clock/count event and underflow when the timer transitions from 0x0000 to
0xFFFF. Just as in overflows, the Overflow/Underflow Flag (TFn) will be set to ‘1’, and an interrupt will
occur if enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RLn
(TMRnCN.0) and the Timer 2, 3, and 4 Run Control bit TRn (TnCON.2) to logic 1. The Timer 2, 3, and 4
respective External Enable EXENn (TnCON.3) must also be set to logic 1 to enable a captures. If EXENn
is cleared, transitions on TnEX will be ignored.
296
External Clock
SYSCLK
(XTAL1)
Tn
TnEX
for further information concerning the configuration of interrupt sources.
Crossbar
8
2
12
Crossbar
EXENn
Figure 24.11. T2, 3, and 4 Capture Mode Block Diagram
TRn
0
1
TMRnCF
Capture
M
T
n
1
M
T
n
0
T
O
G
n
O
E
T
n
Rev. 1.2
TCLK
D
C
N
E
RCAPnL
TMRnL
0xFF
RCAPnH
TMRnH
0xFF
OVF
Toggle Logic
Section “13.3. Interrupt Handler”
CP/RLn
EXENn
EXFn
C/Tn
TRn
TFn
0
1
Interrupt
(Port Pin)
Tn