C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 39

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

4.
MONEN
VREF0
DGND
AGND
XTAL1
XTAL2
Name
AVDD
VREF
/RST
VDD
TMS
TDO
TCK
AV+
TDI
Pinout and Package Definitions
37, 64,
38, 63,
10, 14,
11, 16,
17, 23
F060
F062
100
90
89
24
13
96
97
98
99
26
27
28
21
4
26, 40,
27, 39,
19, 22
Pin Numbers
7, 10,
6, 11,
F061
F063
55
54
18
23
52
53
56
57
58
20
21
63
61
15
37, 64,
38, 63,
11, 16,
10, 14,
17, 23
F064
F066
100
90
89
24
13
96
97
98
99
26
27
28
21
4
26, 40,
27, 39,
19, 22
7, 10,
6, 11,
F065
F067
55
54
18
23
52
53
56
57
58
20
21
63
61
15
Table 4.1. Pin Definitions
D Out JTAG Test Data Output with internal pull-up. Data is
A Out Crystal Output. This pin is the excitation driver for a
A Out Bandgap Voltage Reference Output
D I/O Device Reset. Open-drain output of internal VDD
Type Description
A I/O Bandgap Voltage Reference Output for ADC0.
D In
D In
D In
D In
A In
Rev. 1.2
Digital Supply Voltage. Must be tied to +2.7 to
+3.6 V.
Digital Ground. Must be tied to Ground.
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
Analog Ground. Must be tied to Ground.
JTAG Test Mode Select with internal pull-up.
JTAG Test Clock with internal pull-up.
JTAG Test Data Input with internal pull-up. TDI is
latched on the rising edge of TCK.
shifted out on TDO on the falling edge of TCK. TDO
output is a tri-state driver.
monitor. Is driven low when VDD is <2.7 V and
MONEN is high. An external source can initiate a
system reset by driving this pin low.
Crystal Input. This pin is the return for the internal
oscillator circuit for a crystal or ceramic resonator.
For a precision internal clock, connect a crystal or
ceramic resonator from XTAL1 to XTAL2. If over-
driven by an external CMOS clock, this becomes
the system clock.
crystal or ceramic resonator.
VDD Monitor Enable. When tied high, this pin
enables the internal VDD monitor, which forces a
system reset when VDD is < 2.7 V. When tied low,
the internal VDD monitor is disabled. Recom-
mended configuration is to connect directly to VDD.
ADC0 Voltage Reference Input.
C8051F060/1/2/3/4/5/6/7
39