C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 53

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

5.2.
The voltage reference circuitries for ADC0 and ADC1 allow for many different voltage reference configura-
tions. Each ADC has the capability to use its own dedicated, on-chip voltage reference, or an off-chip refer-
ence circuit. A block diagram of the reference circuitry for one ADC is shown in Figure 5.3.
The internal voltage reference circuit for each ADC consists of an independent, temperature stable 1.2 V
bandgap voltage reference generator, with an output buffer amplifier which multiplies the bandgap refer-
ence by 2. The maximum load seen by the VREFn (VREF0 or VREF1) pin must be less than 100 µA to
AGND. Bypass capacitors of 0.1 µF and 47 µF are recommended from the VREFn pin to VRGNDn.
The voltage reference circuitry for each ADC is controlled in the Reference Control Registers. REF0CN
(defined in Figure 5.11) is the Reference Control Register for ADC0, and REF1CN (defined in Figure 5.12)
is the Reference Control Register for ADC1. The REFnCN registers are used to enable/disable the internal
reference and bias generator circuitry for each ADC independently. The BIASEn bits enable the on-board
bias generators for each ADC, while the REFBEn bits enable the 2x buffer amplifiers which drive the
VREFn pins. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less
than 1 µA (typical) and the output of the buffer amplifier enters a high impedance state (approximately 25 k
Ohms). If the internal voltage reference for an ADC is used, the BIASEn and REFBEn bits for that ADC
must both be set to logic 1. If an external reference is used, the REFBEn bit should be set to logic 0. Note
that the BIASEn bit for an ADC must be set to logic 1 to enable that ADC, regardless of the voltage refer-
ence that is used. If an ADC is not being used, the BIASEn bit can be set to logic 0 to conserve power. The
electrical specifications for the Voltage References are given in Table 5.3.
47F
Bypass Capacitors
Reference
Recommended
Voltage Reference
External
Voltage
0.1F
0.1F
VRGNDn
VBGAPn
VREFn
Figure 5.3. Voltage Reference Block Diagram
Ref
ADCn
Rev. 1.2
Bias
C8051F060/1/2/3/4/5/6/7
x2
Band-Gap
REFnCN
1.25V
EN
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