C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 54

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
5.3.
ADC0 and ADC1 have a maximum conversion speed of 1 Msps. The conversion clocks for the ADCs are
derived from the system clock. The ADCnSC bits in the ADCnCF register determine how many system
clocks (from 1 to 16) are used for each conversion clock.
5.3.1. Starting a Conversion
For ADC0, conversions can be initiated in one of four ways, depending on the programmed states of the
ADC0 Start of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. For ADC0, conversions may be ini-
tiated by:
ADC1 conversions can be initiated in five different ways, according to the ADC1 Start of Conversion Mode
bits (AD1CM2-AD1CM0) in ADC1CN. For ADC1, conversions may be initiated by:
The ADnBUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete.
The falling edge of ADnBUSY triggers an interrupt (when enabled) and sets the ADnINT interrupt flag
(ADCnCN.5). In single-ended mode, the converted data for ADCn is available in the ADCn data word MSB
and LSB registers, ADCnH, ADCnL. In differential mode, the converted data (combined from ADC0 and
ADC1) is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L.
When initiating conversions by writing a ‘1’ to ADnBUSY, the ADnINT bit should be polled to determine
when a conversion has completed (ADCn interrupts may also be used). The recommended polling proce-
dure is shown below.
When an external start-of-conversion source is required in differential mode the two pins (CNVSTR0 and
CNVSTR1) should be tied together.
5.3.2. Tracking Modes
The ADnTM bit in register ADCnCN controls the ADCn track-and-hold mode. When the ADC is enabled,
the ADC input is continuously tracked when a conversion is not in progress. When the ADnTM bit is logic
1, each conversion is preceded by a tracking period (after the start-of-conversion signal). When the
CNVSTRn signal is used to initiate conversions, the ADC will track until a rising edge occurs on the
CNVSTRn pin (see Figure 5.4 and Table 5.1 for conversion timing parameters). Setting ADnTM to 1 can
be useful to ensure that settling time requirements are met when an external multiplexer is used on the
analog input (see
54
ADC Modes of Operation
1. Writing a ‘1’ to the AD0BUSY bit of ADC0CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR0;
4. A Timer 2 overflow (i.e. timed continuous conversions).
1. Writing a ‘1’ to the AD1BUSY bit of ADC1CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR1;
4. A Timer 2 overflow (i.e. timed continuous conversions);
5. Writing a ‘1’ to the AD0BUSY bit of ADC0CN.
Step 1. Write a ‘0’ to ADnINT;
Step 2. Write a ‘1’ to ADnBUSY;
Step 3. Poll ADnINT for ‘1’;
Step 4. Process ADCn data.
Section “5.3.3. Settling Time Requirements” on page
Rev. 1.2
56).