C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 6

• Manufacturer Part Number: C8051F060DK
• Description: DEV KIT FOR F060/F062/F063
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F060DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F06x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F060
• Silicon Family Name: C8051F06x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051060, C8051F062 and C8051F063
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1214

C8051F060/1/2/3/4/5/6/7
19. Controller Area Network (CAN0, C8051F060/1/2/3) ........................................... 225
229
20. System Management BUS / I2C BUS (SMBUS0)................................................ 235
21. Enhanced Serial Peripheral Interface (SPI0)...................................................... 251
6
18.2.Ports 4 through 7 (C8051F060/2/4/6 only) ..................................................... 219
19.1.Bosch CAN Controller Operation.................................................................... 227
19.2.CAN Registers................................................................................................ 228
20.1.Supporting Documents ................................................................................... 236
20.2.SMBus Protocol.............................................................................................. 236
20.3.SMBus Transfer Modes.................................................................................. 238
20.4.SMBus Special Function Registers ................................................................ 241
21.1.Signal Descriptions......................................................................................... 252
21.2.SPI0 Master Mode Operation ......................................................................... 253
21.3.SPI0 Slave Mode Operation ........................................................................... 255
21.4.SPI0 Interrupt Sources ................................................................................... 255
18.1.5.Configuring Port 1 and 2 pins as Analog Inputs..................................... 207
18.1.6.Crossbar Pin Assignment Example........................................................ 208
18.2.1.Configuring Ports which are not Pinned Out .......................................... 219
18.2.2.Configuring the Output Modes of the Port Pins...................................... 219
18.2.3.Configuring Port Pins as Digital Inputs................................................... 219
18.2.4.Weak Pull-ups ........................................................................................ 219
18.2.5.External Memory Interface ..................................................................... 220
19.2.1.CAN Controller Protocol Registers......................................................... 228
19.2.2.Message Object Interface Registers ...................................................... 228
19.2.3.Message Handler Registers................................................................... 228
19.2.4.CIP-51 MCU Special Function Registers ............................................... 229
19.2.5.Using CAN0ADR, CAN0DATH, and CANDATL To Access CAN Registers
19.2.6.CAN0ADR Autoincrement Feature ........................................................ 229
20.2.1.Arbitration............................................................................................... 237
20.2.2.Clock Low Extension.............................................................................. 237
20.2.3.SCL Low Timeout................................................................................... 237
20.2.4.SCL High (SMBus Free) Timeout .......................................................... 237
20.3.1.Master Transmitter Mode ....................................................................... 238
20.3.2.Master Receiver Mode ........................................................................... 238
20.3.3.Slave Transmitter Mode ......................................................................... 239
20.3.4.Slave Receiver Mode ............................................................................. 239
20.4.1.Control Register ..................................................................................... 241
20.4.2.Clock Rate Register ............................................................................... 244
20.4.3.Data Register ......................................................................................... 245
20.4.4.Address Register.................................................................................... 245
20.4.5.Status Register....................................................................................... 246
21.1.1.Master Out, Slave In (MOSI).................................................................. 252
21.1.2.Master In, Slave Out (MISO).................................................................. 252
21.1.3.Serial Clock (SCK) ................................................................................. 252
21.1.4.Slave Select (NSS) ................................................................................ 252
Rev. 1.2