R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 128

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 5 Exception Handling
5.7.2
The exception handling starts when a sleep instruction (SLEEP) is executed while the SSBY bit in
SBYCR is clear (= 0) and the SLPIE bit in SBYCR is set (= 1). The exception handling caused by
execution of a sleep instruction is always executable in the program execution state.
The following operations are performed by the CPU:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the sleep instruction is generated,
After execution of a sleep instruction, a bus master other than the CPU may have bus mastership.
In this case, the exception handling starts at the point when the CPU gets bus mastership after the
operation of the other bus master has ended.
Table 5.9 shows the state of CCR and EXR after execution of illegal instruction exception
handling. See section 24.10, Sleep Instruction Exception Handling, for details.
Table 5.9
[Legend]
1: Set to 1
0: Cleared to 0
: Retains the previous value.
Rev. 2.00 Sep. 16, 2009 Page 98 of 1036
REJ09B0414-0200
Interrupt Control Mode
0
2
the start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
Sleep Instruction
States of CCR and EXR after Sleep Instruction Exception Handling
I
1
1
CCR
UI
0
T
EXR
I2 to I0
7

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