R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 232

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Bus Controller (BSC)
8.6
The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications
can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, CSACR, and
ENDIANCR.
8.6.1
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)
or lower byte data bus (D7 to D0) is used according to the bus specifications for the area being
accessed (8-bit access space or 16-bit access space), the data size, and endian format when
accessing external address space,. For details, see section 8.5.6, Endian and Data Alignment.
8.6.2
Table 8.15 shows the pins used for basic bus interface.
Table 8.15 I/O Pins for Basic Bus Interface
Note:
Rev. 2.00 Sep. 16, 2009 Page 202 of 1036
REJ09B0414-0200
Name
Bus cycle start
Address strobe
Read strobe
Read/write
Low-high write
Low-low write
Chip select 0 to 7
Wait
*
Basic Bus Interface
Data Bus
I/O Pins Used for Basic Bus Interface
When the address/data multiplexed I/O is selected, this pin only functions as the AH
output and does not function as the AS output.
Symbol
BS
AS*
RD
RD/WR
LHWR
LLWR
CS0 to CS7 Output
WAIT
I/O
Output
Output
Output
Output
Output
Output
Input
Function
Signal indicating that the bus cycle has started
Strobe signal indicating that an address output on the
address bus is valid during access
Strobe signal indicating the read access
Signal indicating the data bus input or output
direction
Strobe signal indicating that the upper byte (D15 to
D8) is valid during write access
Strobe signal indicating that the lower byte (D7 to
D0) is valid during write access
Strobe signal indicating that the area is selected
Wait request signal used when an external address
space is accessed