R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 365

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DMAC is activated in
transfer size error state
Extended repeat area
overflow occurs in
source address
DMAC is activated
after BKSZ bits are
changed from 1 to 0
Extended repeat area
overflow occurs in
destination address
Figure 9.40 Procedure Example of Resuming Transfer by Clearing Interrupt Source
[1] Specify the values in the registers such as transfer counter and address register.
[2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or
[3] End the interrupt handling routine by the RTE instruction.
[4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit.
[5] Complete the interrupt handling routine and clear the interrupt mask.
[6] Specify the values in the registers such as transfer counter and address register.
[7] Set the DTE bit to 1 to resume DMA operation.
DARIE bit
SARIE bit
RPTIE bit
ESIF bit in DMDR to 0 and an interrupt source is cleared.
TSIE bit
Interrupt handling routine
Registers are specified
ends (RTE instruction
Transfer end interrupt
Consecutive transfer
DTE bit is set to 1
Transfer resume
handling routine
processing end
processing
executed)
Figure 9.39 Interrupt and Interrupt Sources
[1]
[2]
[3]
Interrupt handling routine
interrupt handling routine
DTIF and ESIF bits are
Registers are specified
Transfer resumed after
DTE bit is set to 1
DTIE bit
Transfer resume
Setting condition is satisfied
DTIF bit
processing end
ESIE bit
ESIF bit
cleared to 0
Rev. 2.00 Sep. 16, 2009 Page 335 of 1036
[Setting condition]
When DTCR becomes 0
and transfer ends
ends
Section 9 DMA Controller (DMAC)
[6]
[4]
[5]
[7]
REJ09B0414-0200
Transfer end
interrupt
Transfer escape
end interrupt