R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 49

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Classification
Bus control
Pin Name
BACK
BS-A/BS-B
AS
AH
RD
RD/WR
LHWR
LLWR
LUB
LLB
CS0
CS1
CS2-A/CS2-B
CS3
CS4
CS5-A/CS5-B
CS6-A/CS6-B
CS7-A/CS7-B
WAIT
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Description
Bus acknowledge signal, which indicates that the bus has
been released.
Indicates the start of a bus cycle.
Strobe signal which indicates that the output address on the
address bus is valid in access to the basic bus interface or
byte control SRAM interface space.
This signal is used to hold the address when accessing the
address-data multiplexed I/O interface space.
Strobe signal which indicates that reading from the basic
bus interface space is in progress.
Indicates the direction (input or output) of the data bus.
Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the basic bus interface
space.
Strobe signal which indicates that the lower-order byte (D7
to D0) is valid in access to the basic bus interface space.
Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the byte control SRAM
interface space.
Strobe signal which indicates that the lower-order byte (D7
to D0) is valid in access to the byte control SRAM interface
space.
Select signals for areas 0 to 7.
Requests wait cycles in access to the external space.
Rev. 2.00 Sep. 16, 2009 Page 19 of 1036
Section 1 Overview
REJ09B0414-0200

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