R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 575

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set
2. Write H'F8 to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to
3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH
4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by
5. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained
13.4.4
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
• At compare match A, the NDR bits are always transferred to PODR.
• At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are
Figure 13.6 illustrates the non-overlapping pulse output operation.
Pulse
output pin
a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in
TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.
select compare match in the TPU channel set up in the previous step to be the output trigger.
Write output data H'80 in NDRH.
contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the
next output data (H'C0) in NDRH.
writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts.
without imposing a load on the CPU.
not transferred if their value is 1.
Non-Overlapping Pulse Output
Figure 13.6 Non-Overlapping Pulse Output
Normal output/inverted output
Q
NDER
Q
PODR
C
D
Section 13 Programmable Pulse Generator (PPG)
Rev. 2.00 Sep. 16, 2009 Page 545 of 1036
Q
NDR
Compare match A
Compare match B
D
REJ09B0414-0200
Internal data bus