R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 717

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
7
6
5
4
3
2
1
0
Bit Name
BBSY
SCP
SDAO

SCLO

IICRST

0
Initial
Value
0
1
1
1
1
1
1
R/W
R/W
R/W
R
R/W
R

R/W

Description
Bus Busy
This bit indicates whether the I
released and to issue start and stop conditions in
master mode. This bit is set to 1 when the SDA level
changes from high to low under the condition of SCL =
high, assuming that the start condition has been
issued. This bit is cleared to 0 when the SDA level
changes from low to high under the condition of SDA =
high, assuming that the stop condition has been
issued. Follow this procedure also when re-transmitting
a start condition. To issue a start or stop condition, use
the MOV instruction.
Start/Stop Condition Issue
This bit controls the issuance of start or stop condition
in master mode.
To issue a start condition, write 1 to BBSY and 0 to
SCP. A re-transmit start condition is issued in the same
way. To issue a stop condition, write 0 to BBSY and 0
to SCP. This bit is always read as 1. If 1 is written, the
data is not stored.
This bit monitors the output level of SDA.
0: When reading, the SDA pin outputs a low level
1: When reading the SDA pin outputs a high level
Reserved
The write value should always be 1.
This bit monitors the SCL output level.
When reading and SCLO is 1, the SCL pin outputs a
high level. When reading and SCLO is 0, the SCL pin
outputs a low level.
Reserved
This bit is always read as 0.
IIC Control Module Reset
This bit reset the IIC control module except the I
registers. If hang-up occurs because of communication
failure during I
Reserved
This bit is always read as 1.
2
C operation, by setting this bit to 1, the
Rev. 2.00 Sep. 16, 2009 Page 687 of 1036
Section 17 I
2
C bus is occupied or
2
C Bus Interface 2 (IIC2)
REJ09B0414-0200
2
C