R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 732

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 17 I
17.4.4
In slave transmit mode, the slave device outputs the transmit data, and the master device outputs
the receive clock pulse and returns an acknowledge signal. Figures 17.9 and 16.10 show the
operation timings in slave transmit mode. The transmission procedure and operations in slave
transmit mode are described below.
1. Set the ICR bit in the corresponding register to 1, then set the ICE bit in ICCRA to 1. Set the
2. When the slave address matches in the first frame following the detection of the start
3. If TDRE is set after writing the last transmit data to ICDRT, wait until TEND in ICSR is set to
4. Clear TRS for end processing, and read ICDRR (dummy read) to free SCL.
5. Clear TDRE.
Rev. 2.00 Sep. 16, 2009 Page 702 of 1036
REJ09B0414-0200
(Master output)
(Master output)
(Slave output)
processing
ACKBIT in ICIER, and perform other initial settings. Set the MST and TRS bits in ICCRA to
select slave receive mode, and wait until the slave address matches.
condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the
rising of the ninth clock pulse. At this time, if the eighth bit data (R/W) is 1, TRS in ICCRA
and TDRE in ICSR are set to 1, and the mode changes to slave transmit mode automatically.
The continuous transmission is performed by writing the transmit data to ICDRT every time
TDRE is set.
1, with TDRE = 1. When TEND is set, clear TEND.
ICDRS
ICDRR
RCVD
RDRF
User
SDA
SDA
SCL
Slave Transmit Operation
2
C Bus Interface 2 (IIC2)
Data n-1
[5] Set RCVD then read ICDRR
Figure 17.8 Master Receive Mode Operation Timing 2
A
9
Data n-1
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
[6] Issue stop condition [7] Read ICDRR and clear RCVD
4
Bit 3
5
Bit 2
6
Bit 1
7
Data n
Bit 0
8
A/A
9
[8] Set slave receive mode
Data n

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