R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 814

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 22 Flash Memory
(2)
The on-chip program is automatically downloaded by setting the flash key code register (FKEY)
and the SCO bit in the flash code control/status register (FCCS) after initializing the vector base
register (VBR). The memory MAT is replaced with the embedded program storage area during
download. Since the memory MAT cannot be read during programming/erasing, the procedure
program must be executed in a space other than the flash memory (for example, on-chip RAM).
Since the download result is returned to the programming/erasing interface parameter, whether
download is normally executed or not can be confirmed. The VBR contents can be changed after
completion of download.
(3)
A pulse with the specified period must be applied when programming or erasing. The specified
pulse width is made by the method in which wait loop is configured by the CPU instruction.
Accordingly, the operating frequency of the CPU needs to be set before programming/erasure. The
operating frequency of the CPU is set by the programming/erasing interface parameter.
(4)
The start address of the programming destination and the program data are specified in 128-byte
units when programming. The block to be erased is specified with the erase block number in
erase-block units when erasing. Specifications of the start address of the programming destination,
program data, and erase block number are performed by the programming/erasing interface
parameters, and the on-chip program is initiated. The on-chip program is executed by using the
JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip
RAM. The execution result is returned to the programming/erasing interface parameter.
The area to be programmed must be erased in advance when programming flash memory. All
interrupts are disabled during programming/erasure.
(5)
When processing does not end by 128-byte programming or 1-block erasure, consecutive
programming/erasure can be realized by updating the start address of the programming destination
and program data, or the erase block number. Since the downloaded on-chip program is left in the
on-chip RAM even after programming/erasure completes, download and initialization are not
required when the same processing is executed consecutively.
Rev. 2.00 Sep. 16, 2009 Page 784 of 1036
REJ09B0414-0200
Download of On-Chip Program
Initialization of Programming/Erasure
Execution of Programming/Erasure
When Programming/Erasure is Executed Consecutively