C8051F330-TB Silicon Laboratories Inc, C8051F330-TB Datasheet
C8051F330-TB
Specifications of C8051F330-TB
Related parts for C8051F330-TB
C8051F330-TB Summary of contents
Page 1
... HIGH-SPEED CONTROLLER CORE 2/4/8 kB 8051 CPU (25 MIPS) DEBUG CIRCUITRY Copyright © 2010 by Silicon Laboratories C8051F330/1/2/3/4/5 Mixed-Signal ISP Flash MCU 24.5 MHz with ±2% accuracy supports crystal-less UART operation 80/40/20/10 kHz low frequency, low power Port 0 Port 1 P2.0 768 B SRAM POR WDT C8051F330/1/2/3/4/5 ...
Page 2
... C8051F330/1/2/3/4/5 2 Rev. 1.7 ...
Page 3
... Settling Time Requirements ..................................................................... 46 5.4. Programmable Window Detector ...................................................................... 51 5.4.1. Window Detector In Single-Ended Mode ................................................. 53 5.4.2. Window Detector In Differential Mode...................................................... 54 6. 10-Bit Current Mode DAC (IDA0, C8051F330 only).............................................. 57 6.1. IDA0 Output Scheduling ................................................................................... 57 6.1.1. Update Output On-Demand ..................................................................... 57 6.1.2. Update Output Based on Timer Overflow ................................................ 58 6.1.3. Update Output Based on CNVSTR Edge................................................. 58 6 ...
Page 4
... C8051F330/1/2/3/4/5 9.2.5. Stack ....................................................................................................... 78 9.2.6. Special Function Registers....................................................................... 79 9.2.7. Register Descriptions ............................................................................... 83 9.3. Interrupt Handler ............................................................................................... 85 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 86 9.3.2. External Interrupts .................................................................................... 87 9.3.3. Interrupt Priorities ..................................................................................... 87 9.3.4. Interrupt Latency ...................................................................................... 87 9.3.5. Interrupt Register Descriptions................................................................. 89 9.4. Power Management Modes .............................................................................. 94 9.4.1. Idle Mode.................................................................................................. 94 9.4.2. Stop Mode ................................................................................................ 95 10 ...
Page 5
... Special Function Registers ...................................................................... 169 18. Timers.................................................................................................................... 177 18.1.Timer 0 and Timer 1 ....................................................................................... 177 18.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 177 18.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 178 18.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 179 18.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 180 18.2.Timer 2 .......................................................................................................... 185 18.2.1.16-bit Timer with Auto-Reload................................................................ 185 C8051F330/1/2/3/4/5 Rev. 1.7 5 ...
Page 6
... C8051F330/1/2/3/4/5 18.2.2.8-bit Timers with Auto-Reload................................................................ 186 18.3.Timer 3 .......................................................................................................... 189 18.3.1.16-bit Timer with Auto-Reload................................................................ 189 18.3.2.8-bit Timers with Auto-Reload................................................................ 190 19. Programmable Counter Array ............................................................................. 193 19.1.PCA Counter/Timer ........................................................................................ 194 19.2.Capture/Compare Modules ............................................................................ 195 19.2.1.Edge-triggered Capture Mode................................................................ 196 19.2.2.Software Timer (Compare) Mode........................................................... 197 19.2.3.High-Speed Output Mode ...................................................................... 198 19 ...
Page 7
... Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 53 Figure 5.7. ADC Window Compare Example: Right-Justified Differential Data ....... 54 Figure 5.8. ADC Window Compare Example: Left-Justified Differential Data ......... 54 6. 10-Bit Current Mode DAC (IDA0, C8051F330 only) Figure 6.1. IDA0 Functional Block Diagram............................................................. 57 Figure 6.2. IDA0 Data Word Mapping...................................................................... 58 7 ...
Page 8
... C8051F330/1/2/3/4/5 Figure 10.2. Power-On and VDD Monitor Reset Timing .......................................... 98 11. Flash Memory Figure 11.1. Flash Program Memory Map.............................................................. 105 12. External RAM 13. Oscillators Figure 13.1. Oscillator Diagram.............................................................................. 113 Figure 13.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram . 119 14. Port Input/Output Figure 14.1. Port I/O Functional Block Diagram ..................................................... 123 Figure 14 ...
Page 9
... Figure 19.7. PCA Frequency Output Mode ............................................................ 199 Figure 19.8. PCA 8-Bit PWM Mode Diagram ......................................................... 200 Figure 19.9. PCA 16-Bit PWM Mode...................................................................... 201 Figure 19.10. PCA Module 2 with Watchdog Timer Enabled ................................. 202 20. C2 Interface Figure 20.1. Typical C2 Pin Sharing....................................................................... 211 C8051F330/1/2/3/4/5 Rev. 1.7 9 ...
Page 10
... Table 3.1. Global Electrical Characteristics ............................................................. 32 Table 3.2. Index to Electrical Characteristics Tables............................................... 34 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5........................................... 35 Table 4.2. QFN-20 Package Dimensions ................................................................ 38 Table 4.3. QFN-20 PCB Land Pattern Dimesions ................................................... 39 5. 10-Bit ADC (ADC0, C8051F330/2/4 only) Table 5 ...
Page 11
... C8051F330/1/2/3/4/5 Table 16.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator .............................................................. 160 Table 16.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ........................................................ 161 Table 16.4. Timer Settings for Standard Baud Rates Using an ...
Page 12
... SFR Definition 13.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 117 SFR Definition 13.5. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 SFR Definition 14.1. XBR0: Port I/O Crossbar Register 128 SFR Definition 14.2. XBR1: Port I/O Crossbar Register 129 SFR Definition 14.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 C8051F330/1/2/3/4/5 Rev. 1.7 13 ...
Page 13
... C8051F330/1/2/3/4/5 SFR Definition 14.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SFR Definition 14.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 131 SFR Definition 14.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SFR Definition 14.7. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SFR Definition 14.8. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 SFR Definition 14.9. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 132 SFR Definition 14 ...
Page 14
... C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 210 C2 Register Definition 20.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 210 C8051F330/1/2/3/4/5 Rev. 1.7 15 ...
Page 15
... Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals The C8051F330/1/2/3/4/5 are available in 20-pin QFN packages (also referred to as MLP or MLF packages). Lead-free (RoHS compliant) packages are also available ...
Page 16
... C8051F330/1/2/3/4/5 Table 1.1. Product Selection Guide C8051F330- 768 C8051F331- 768 C8051F332- 768 C8051F333- 768 C8051F334- 768 C8051F335- 768 18 — — — — ...
Page 17
... Reset RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24.5 MHz (2%) Internal Oscillator 80 kHz Internal Oscillator Figure 1.1. C8051F330 Block Diagram Analog/Digital VDD Power GND C2D Debug HW Reset RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24 ...
Page 18
... C8051F330/1/2/3/4/5 Analog/Digital VDD Power GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24.5 MHz (2%) Internal Oscillator 80 kHz Internal Oscillator Figure 1.3. C8051F332 Block Diagram Analog/Digital VDD Power GND C2D Debug HW Reset /RST/C2CK Brown- POR ...
Page 19
... C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24.5 MHz (2%) Internal Oscillator 80 kHz Internal Oscillator Figure 1.6. C8051F335 Block Diagram C8051F330/1/2/3/4/5 Port 0 Latch UART Timer 3-Chnl PCA WDT 8 FLASH SMBus 0 SPI 256 byte 5 SRAM Port 1 1 ...
Page 20
... CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F330/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, ...
Page 21
... Additional Features The C8051F330/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and periph- erals to improve performance and ease of use in end applications. The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as opposed to 7 for the stan- dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...
Page 22
... Program memory consists of 2/4 Flash. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. See Figure 1.9 for the MCU system mem- ory map. C8051F330/1 PROGRAM/DATA MEMORY (FLASH) RESERVED ...
Page 23
... All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them synchronized. The C8051F330DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F330/1/2/3/4/5 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and a debug adapter ...
Page 24
... C8051F330/1/2/3/4/5 devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The C8051F330/1/2/3/4/5 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be config- ured for push-pull or open-drain output. The “ ...
Page 25
... Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system reset, Module 2 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. Capture/Compare Figure 1.13. PCA Block Diagram C8051F330/1/2/3/4/5 SYSCLK/12 SYSCLK/4 Timer 0 Overflow PCA ...
Page 26
... Analog to Digital Converter The C8051F330/2/4 devices include an on-chip 10-bit SAR ADC with a 16-channel differential input multi- plexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and DNL of ±1 LSB. The ADC system includes a configurable analog multiplexer that selects both positive and nega- tive ADC inputs. Ports0-1 are available as an ADC inputs ...
Page 27
... Comparators C8051F330/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and config- ured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchro- nous) output. Comparator response time is programmable, allowing the user to select between high-speed and low-power modes ...
Page 28
... Current Output DAC The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximum current output of the IDA0 can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and sup- ports jitter-free updates for waveform generation ...
Page 29
... Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051F330/1/2/3/4/5 Conditions Min –55 – ...
Page 30
... C8051F330/1/2/3/4/5 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Voltage Digital Supply RAM Data Retention Voltage SYSCLK (System Clock) (Note 2) T (SYSCLK High Time) SYSH T (SYSCLK Low Time) SYSL Specified Operating ...
Page 31
... For example MHz) * 0.15 mA/MHz = 1.8 mA. Other electrical characteristics tables are found in the data sheet section corresponding to the associated peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page indicated in Table 3.2. C8051F330/1/2/3/4/5 Conditions Min = 3 MHz — ...
Page 32
... C8051F330/1/2/3/4/5 Table 3.2. Index to Electrical Characteristics Tables Peripheral Electrical Characteristics ADC0 Electrical Characteristics IDAC Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Reset Electrical Characteristics Flash Electrical Characteristics Internal Oscillator Electrical Characteristics Port I/O DC Electrical Characteristics 34 Rev. 1.7 Page No. ...
Page 33
... Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5 Pin Pin Name ‘F330/1/2/ ’F330-GP 3/4/5- GND 2 5 RST C2CK P2. C2D P0. VREF P0 IDA0 P0. XTAL1 P0. XTAL2 P0 P0 C8051F330/1/2/3/4/5 Type Description Power Supply Voltage. Ground. D I/O Device Reset. Open-drain output of internal POR or V monitor. An external source can initiate a system reset by driving this pin low for at least 10 µ ...
Page 34
... C8051F330/1/2/3/4/5 Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5 (Continued) Pin Pin Name ‘F330/1/2/ ’F330-GP 3/4/5-GM P0. CNVSTR Type Description D I/O or Port 0.6. See Section ADC0 External Convert Start or IDA0 Update Source Input. See Section 5 and Section 6 D I/O or Port 0 ...
Page 35
... P0.0 1 GND 2 C8051F330/1/2/3/4/5-GM VDD 3 /RST/C2CK 4 P2.0/C2D 5 Figure 4.1. QFN-20 Pinout Diagram (Top View) C8051F330/1/2/3/4/5 Top View GND Rev. 1.7 15 P0.6 14 P0.7 13 P1.0 12 P1.1 11 P1.2 37 ...
Page 36
... C8051F330/1/2/3/4/5 Figure 4.2. QFN-20 Package Drawing Table 4.2. QFN-20 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 b 0.18 0.23 D 4.00 BSC. D2 2.00 2.15 e 0.50 BSC. E 4.00 BSC. E2 2.00 2.15 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
Page 37
... A 2x2 array of 0.95 mm openings on a 1.1 mm pitch should be used for the center pad to assure the proper paste volume (71% Paste Coverage). Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. C8051F330/1/2/3/4/5 Dimension Min X2 2.15 Y1 ...
Page 38
... ADC (ADC0, C8051F330/2/4 only) The ADC0 subsystem for the C8051F330/2/4 consists of two analog multiplexers (referred to collectively as AMUX0) with 16 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5 ...
Page 39
... C8051F330/1/2/3/4/5 measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justified and left- justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’. Input Voltage Right-Justified ADC0H:ADC0L VREF x 1023/1024 VREF x 512/1024 VREF x 256/1024 0 When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers. ...
Page 40
... Figure 5.2. Typical Temperature Sensor Transfer Function 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 AD0SC 31). C8051F330/1/2/3/4 2.86(TEMP TEMP 0 50 Rev ...
Page 41
... C8051F330/1/2/3/4/5 5.3.1. Starting a Conversion A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol- lowing: 1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN 2. A Timer 0 overflow (i.e., timed continuous conversions) 3 ...
Page 42
... Timer 0, Timer 2, Timer 1, Timer 3 Overflow (AD0CM[2:0]=000, 001,010 011, 101) SAR Clocks Low Power AD0TM=1 or Convert SAR Clocks Track or AD0TM=0 Convert Figure 5.3. 10-Bit ADC Track and Conversion Example Timing C8051F330/1/2/3/4/5 Section “5.3.3. Settling Time Requirements” on page Track Convert Convert ...
Page 43
... C8051F330/1/2/3/4/5 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accu- racy required for the conversion ...
Page 44
... C8051F330/1/2/3/4/5 R/W R/W R/W R/W AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 Bit2 Bit1 ADC0 Positive Input P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0 ...
Page 45
... C8051F330/1/2/3/4/5 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode. For all other Negative Input selections, ADC0 operates in Differential mode. ...
Page 46
... Bits7–0: ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always read ‘0’. C8051F330/1/2/3/4/5 R/W R/W R/W ...
Page 47
... C8051F330/1/2/3/4/5 SFR Definition 5.6. ADC0CN: ADC0 Control R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. ...
Page 48
... Bits7–0: High byte of ADC0 Greater-Than Data Word SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Greater-Than Data Word C8051F330/1/2/3/4/5 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W ...
Page 49
... C8051F330/1/2/3/4/5 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: High byte of ADC0 Less-Than Data Word SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Less-Than Data Word ...
Page 50
... ADC0LTH:ADC0LTL 0x1FC0 0x1040 VREF x (64/1024) 0x1000 ADC0GTH:ADC0GTL 0x0FC0 AD0WINT not affected 0x0000 0 Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data C8051F330/1/2/3/4/5 ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF 0x0081 VREF x (128/1024) 0x0080 0x007F AD0WINT=1 0x0041 VREF x (64/1024) 0x0040 ...
Page 51
... C8051F330/1/2/3/4/5 5.4.2. Window Detector In Differential Mode Figure 5.7 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (–1d). In differential mode, the measurable voltage between the input pins is between –VREF and VREF x (511/512). Output codes are represented as 10-bit 2s complement signed integers ...
Page 52
... Gain Error* Offset Temp = 0 °C Offset Error* Power Supply Current Operating Mode, 200 ksps (V supplied to ADC0) DD Power Supply Rejection *Note: Represents one standard deviation from the mean. C8051F330/1/2/3/4/5 – +85 °C unless otherwise specified. Conditions Min DC Accuracy — — -15 -15 — ...
Page 53
... C8051F330/1/2/3/4/5 56 Rev. 1.7 ...
Page 54
... Current Mode DAC (IDA0, C8051F330 only) The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maximum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see SFR Definition 6.1). ...
Page 55
... C8051F330/1/2/3/4/5 6.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen- dently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event. This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘ ...
Page 56
... SFR Definition 6.2. IDA0H: IDA0 Data Word MSB R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: IDA0 Data Word High-Order Bits. Bits 7–0 are the most-significant bits of the 10-bit IDA0 Data Word. C8051F330/1/2/3/4 Bit4 Bit3 Bit2 ...
Page 57
... C8051F330/1/2/3/4/5 SFR Definition 6.3. IDA0L: IDA0 Data Word LSB R/W R/W R — Bit7 Bit6 Bit5 Bits 7–6: IDA0 Data Word Low-Order Bits. Lower 2 bits of the 10-bit Data Word. Bits 5–0: UNUSED. Read = 000000b, Write = don’t care. Table 6.1. IDAC Electrical Characteristics – ...
Page 58
... Voltage Reference (C8051F330/2/4 only) The Voltage reference MUX on the C8051F330/2/4 devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the V Figure 7.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For an external source or the internal reference, REFSL should be set to ‘0’. To use V source, REFSL should be set to ‘ ...
Page 59
... C8051F330/1/2/3/4/5 SFR Definition 7.1. REF0CN: Reference Control Bit7 Bit6 Bit5 Bits7–4: UNUSED. Read = 0000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference used as voltage reference. ...
Page 60
... Input Current 3.0 V BIASE = ‘1’ or AD0EN = ‘1’ or ADC Bias Generator IOSCEN = ‘1’ REFBE = ‘1’ or TEMPE = ‘1’ or Reference Bias Generator IDA0EN = ‘1’ C8051F330/1/2/3/4/5 Conditions Min Internal Reference (REFBE = 1) 2.38 External Reference (REFBE = 0) Power Specifications Rev. 1.7 ...
Page 61
... C8051F330/1/2/3/4/5 64 Rev. 1.7 ...
Page 62
... Comparator0 C8051F330/1/2/3/4/5 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 8.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 asyn- chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when in when the system clock is not active ...
Page 63
... C8051F330/1/2/3/4/5 The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis- abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to less than 100 nA ...
Page 64
... Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051F330/1/2/3/4/5 R/W R/W R/W CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 Bit4 Bit3 Bit2 Rev ...
Page 65
... C8051F330/1/2/3/4/5 SFR Definition 8.2. CPT0MX: Comparator0 MUX Selection R/W R/W R/W CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 Bit7 Bit6 Bit5 Bits7–4: CMX0N3–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. ...
Page 66
... Comparator0 Falling-edge interrupt enabled. Bits3–2: UNUSED. Read = 00b, Write = don’t care. Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. Mode CP0MD1 CP0MD0 C8051F330/1/2/3/4 CP0MD1 CP0MD0 00000010 Bit4 Bit3 Bit2 Bit1 CP0 Response Time (TYP) 0 ...
Page 67
... C8051F330/1/2/3/4/5 Table 8.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter CP0+ – CP0– = 100 mV Response Time: * Mode 0, Vcm = 1.5 V CP0+ – CP0– = –100 mV CP0+ – CP0– = 100 mV Response Time: * Mode 1, Vcm = 1.5 V CP0+ – CP0– = –100 mV CP0+ – ...
Page 68
... ACCUMULATOR RESET CLOCK STOP IDLE Figure 9.1. CIP-51 Block Diagram C8051F330/1/2/3/4/5 Section 18), an enhanced full-duplex UART (see description Section 17), 256 bytes of internal RAM, 128 byte (Section 9.2.6), and 17 Port I/O (see description in - 256 Bytes of Internal RAM ...
Page 69
... MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F330/1/2/3/4/5 does not support off-chip data or program memory). In the CIP-51, the MOVX instruction can be used to access on-chip XRAM or on-chip program memory space implemented as re-programmable Flash mem- ory ...
Page 70
... ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A C8051F330/1/2/3/4/5 Section “11. Flash Memory” on page 103 Description Arithmetic Operations Logical Operations Rev. 1.7 Bytes Clock Cycles ...
Page 71
... C8051F330/1/2/3/4/5 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A ...
Page 72
... CJNE Rn, #data, rel equal Compare immediate to indirect and jump if not CJNE @Ri, #data, rel equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation C8051F330/1/2/3/4/5 Description Program Branching Rev. 1.7 Bytes Clock Cycles ...
Page 73
... C8051F330/1/2/3/4/5 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. ...
Page 74
... Byte Sectors) 0x0000 9.2.1. Program Memory The CIP-51 core has program memory space. The C8051F330/1 implements this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x1DFF. Addresses above 0x1DFF are reserved on the 8 kB devices. The C8051F332/3 and C8051F334/5 implement, in contiguous blocks, 2 and 4 kB, from addresses 0x0000 to 0x07FF or 0x0000 to 0x0FFF, respectively ...
Page 75
... C8051F330/1/2/3/4/5 9.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca- tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...
Page 76
... SPI0CFG SPI0CKR 98 SCON0 SBUF0 90 P1 TMR3CN TMR3RLL TMR3RLH 88 TCON TMOD TL0 DPL 0(8) 1(9) 2(A) (bit addressable) C8051F330/1/2/3/4/5 PCA0CPL0 PCA0CPH0 OSCLCN IT01CF P0SKIP P1SKIP TMR2L TMR2H AMX0P ADC0CF ADC0L OSCICL SPI0DAT P0MDOUT P1MDOUT P2MDOUT CPT0CN CPT0MD TMR3L TMR3H TL1 TH0 TH1 ...
Page 77
... C8051F330/1/2/3/4/5 Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 Greater-Than Compare Low ...
Page 78
... Reset Source Configuration/Status SBUF0 0x99 UART0 Data Buffer SCON0 0x98 UART0 Control SMB0CF 0xC1 SMBus Configuration SMB0CN 0xC0 SMBus Control SMB0DAT 0xC2 SMBus Data C8051F330/1/2/3/4/5 Description Rev. 1.7 Page 117 130 130 131 131 131 132 132 132 133 133 205 ...
Page 79
... C8051F330/1/2/3/4/5 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SP 0x81 Stack Pointer SPI0CFG 0xA1 SPI Configuration SPI0CKR 0xA2 SPI Clock Rate Control SPI0CN 0xF8 SPI Control SPI0DAT 0xA3 SPI Data ...
Page 80
... R/W R/W Bit7 Bit6 Bit5 Bits7–0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. C8051F330/1/2/3/4/5 R/W R/W R/W R/W Bit4 Bit3 Bit2 ...
Page 81
... C8051F330/1/2/3/4/5 SFR Definition 9.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared to logic 0 by all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition borrow from (subtraction) the high order nibble ...
Page 82
... Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. Note: Any instruction that clears the EA bit should be immediately followed by an instruction that has two or more opcode bytes. For example 'C': clear EA bit. C8051F330/1/2/3/4/5 R/W R/W R/W R/W ACC.4 ACC ...
Page 83
... C8051F330/1/2/3/4 this is a dummy instruction with two-byte opcode. assembly: CLR EA ; clear EA bit. CLR EA ; this is a dummy instruction with two-byte opcode interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. How- ever, a read of the EA bit will return a '0' inside the interrupt service routine. When the " ...
Page 84
... DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. C8051F330/1/2/3/4/5 (Section “18.1. Timer 0 and Timer 1” on page IT1 ...
Page 85
... C8051F330/1/2/3/4/5 Table 9.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 0x0003 (/INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (/INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B RESERVED 0x0043 ADC0 Window Compare 0x004B ADC0 Conversion ...
Page 86
... Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. Bit0: EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. C8051F330/1/2/3/4/5 R/W R/W R/W R/W ES0 ET1 ...
Page 87
... C8051F330/1/2/3/4/5 SFR Definition 9.8. IP: Interrupt Priority R R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. ...
Page 88
... Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT). Bit1: RESERVED. Read = 0. Must Write 0. Bit0: ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. C8051F330/1/2/3/4/5 R/W R/W R/W EPCA0 EADC0 EWADC0 Reserved Bit4 ...
Page 89
... C8051F330/1/2/3/4/5 SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 Reserved PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. ...
Page 90
... IN0SL2–0 /INT0 Port Pin 000 P0.0 001 P0.1 010 P0.2 011 P0.3 100 P0.4 101 P0.5 110 P0.6 111 P0.7 C8051F330/1/2/3/4/5 R/W R/W R/W IN1SL0 IN0PL IN0SL2 IN0SL1 Bit4 Bit3 Bit2 Rev. 1.7 R/W R/W Reset Value IN0SL0 00000001 Bit1 ...
Page 91
... C8051F330/1/2/3/4/5 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states ...
Page 92
... IDLE: Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) C8051F330/1/2/3/4/5 R/W R/W R/W ...
Page 93
... C8051F330/1/2/3/4/5 96 Rev. 1.7 ...
Page 94
... Px.x C0RSEF Missing Clock Detector (one- shot) EN System Clock CIP-51 Microcontroller Core Figure 10.1. Reset Sources C8051F330/1/2/3/4/5 for information on selecting and configuring details the use of the Watchdog Timer). VDD Power On Supply Monitor ' Enable PCA (Software Reset) WDT SWRSF EN System Reset Rev ...
Page 95
... C8051F330/1/2/3/4/5 10.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the V RST increases (V ramp time is defined as how fast V DD power-on and V monitor reset timing ...
Page 96
... MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise, this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables it. The state of the RST pin is unaffected by this reset. C8051F330/1/2/3/4/5 monitor. DD ...
Page 97
... C8051F330/1/2/3/4/5 10.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non- inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘ ...
Page 98
... Read: Last reset was not a power- reset source. 1: Read: Last reset was a power- indeterminate. Write Bit0: PINRSF: HW Pin Reset Flag. 0: Source of last reset was not RST pin. 1: Source of last reset was RST pin. C8051F330/1/2/3/4/5 R/W R R/W R/W WDTRSF MCDRSF PORSF Bit4 Bit3 ...
Page 99
... C8051F330/1/2/3/4/5 Table 10.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I OL RST Output Low Voltage V DD RST Input High Voltage RST Input Low Voltage RST Input Pullup Current RST = 0 POR Threshold ( RST Missing Clock Detector Time- Time from last system clock ...
Page 100
... Step 4. Write the first key code to FLKEY: 0xA5. Step 5. Write the second key code to FLKEY: 0xF1. Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE and PSEE bits. C8051F330/1/2/3/4/5 Section “20. C2 Interface” Rev. 1.7 Monitor DD ...
Page 101
... Steps 5–7 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be cleared so that MOVX instructions do not target program memory. Table 11.1. Flash Electrical Characteristics V – = 2 +85 ºC unless otherwise specified. DD Parameter C8051F330/1 Flash Size C8051F332/3 C8051F334/5 Endurance Erase Cycle Time 25 MHz System Clock Write Cycle Time 25 MHz System Clock *Note: 512 bytes at addresses 0x1E00 to 0x1FFF are reserved ...
Page 102
... Unlocked FLASH Pages Access limit set according to the FLASH security lock byte Locked Flash Pages Figure 11.2. Flash Program Memory Map C8051F330/1/2/3/4/5 11111101b 00000010b 3 (First two Flash pages + Lock Byte Page) 0x0FFF or 0x0600 to 0x07FF (Lock Byte Page) C8051F332/3 Reserved 0x1E00 ...
Page 103
... C8051F330/1/2/3/4/5 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Table 11.2 summarizes the Flash security features of the 'F330/1/2/3/4/5 devices ...
Page 104
... Silicon Laboratories web site. 9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser- C8051F330/1/2/3/4/5 monitor DD rise time specification met. If the system cannot ...
Page 105
... C8051F330/1/2/3/4/5 viced in priority order after the Flash operation has been completed and interrupts have been re-enabled by software. 10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your compiler documentation for instructions regarding how to explicitly locate variables in dif- ferent memory areas ...
Page 106
... Flash reads. At system clock frequen- cies below 10 MHz, disabling the Flash one-shot will increase system power consumption. 0: Flash one-shot disabled. 1: Flash one-shot enabled. Bits6–0: RESERVED. Read = 0. Must Write 0. C8051F330/1/2/3/4/5 R/W R/W R/W R/W ...
Page 107
... External RAM The C8051F330/1/2/3/4/5 devices include 512 bytes of RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in SFR Definition 12 ...
Page 108
... C8051F330/1/2/3/4/5 112 Rev. 1.7 ...
Page 109
... The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 13.1. On C8051F330/1/2/3/4/5 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency. Electrical specifications for the precision internal oscillator are given in Table 13.1 on page 122. Note that the system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN ...
Page 110
... This register determines the internal oscillator period. When set to 0000000b, the H-F oscil- lator operates at its fastest setting. When set to 1111111b, the H-F oscillator operates at its slowest setting. On C8051F330/1/2/3/4/5 devices, the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz. ...
Page 111
... Programmable Internal Low-Frequency (L-F) Oscillator All C8051F330/1/2/3/4/5 devices include a programmable low-frequency internal oscillator, which is cali- brated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock using the OSCLD bits in the OSCLCN register (see SFR Defi- nition 13.3). Additionally, the OSCLF bits (OSCLCN5:2) can be used to adjust the oscillator’ ...
Page 112
... C8051F330/1/2/3/4/5 13.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 13. M ...
Page 113
... R = Pullup resistor value in k C MODE (Circuit from Figure 13.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired where frequency of clock in MHz C = capacitor value the XTAL2 pin Power Supply on MCU in volts DD C8051F330/1/2/3/4/5 R/W R R/W R/W - XFCN2 XFCN1 Bit4 Bit3 Bit2 ...
Page 114
... C8051F330/1/2/3/4/5 13.3.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 13.4 (OSCXCN register). For example ...
Page 115
... XTAL pins should equal 25 pF. With a stray capacitance per pin, the 22 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 13.2. 32.768 kHz 22pF* * Capacitor values depend on crystal specifications Figure 13.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram C8051F330/1/2/3/4/5 XTAL1 10M XTAL2 22pF* Rev. 1.7 119 ...
Page 116
... C8051F330/1/2/3/4/5 13.3.2. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter- mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation ...
Page 117
... Bits1–0: CLKSL[1:0]: System Clock Source Select Bits. 00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN bits in register OSCICN. 01: SYSCLK derived from the External Oscillator circuit. 10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the OSCLD bits in register OSCLCN. 11: reserved. C8051F330/1/2/3/4 R ...
Page 118
... C8051F330/1/2/3/4/5 Table 13.1. Internal Oscillator Electrical Characteristics V = 2 –40 to +85 °C unless otherwise specified DD A Parameter Internal High-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency IFCN = 11b Oscillator Supply Current 25 °C, V (from OSCICN Power Supply Sensitivity Constant Temperature Temperature Sensitivity ...
Page 119
... SPI 2 SMBus 2 CP0 Outputs SYSCLK 4 PCA 2 Lowest T0, T1 Priority 8 P0 (P0.0-P0. (P1.0-P1.7) Figure 14.1. Port I/O Functional Block Diagram C8051F330/1/2/3/4/5 XBR0, XBR1, PnMDOUT, PnSKIP Registers PnMDIN Registers Priority Decoder P0 8 I/O Cells P1 Digital 8 I/O Crossbar Cells Rev. 1.7 P0.0 P0.7 P1.0 P1 ...
Page 120
... C8051F330/1/2/3/4/5 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 14.2. Port I/O Cell Block Diagram 124 VDD VDD (WEAK) GND Rev. 1.7 PORT PAD ...
Page 121
... P0SKIP[0:7] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the crossbar. When these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins. Figure 14.3. Crossbar Priority Decoder with No Pins Skipped C8051F330/1/2/3/4/5 P0 CNVSTR ...
Page 122
... C8051F330/1/2/3/4/5 SF Signals VREF IDA x1 x2 PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI P0SKIP[0:7] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the crossbar. When these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins ...
Page 123
... Table alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. C8051F330/1/2/3/4/5 Rev. 1.7 127 ...
Page 124
... C8051F330/1/2/3/4/5 SFR Definition 14.1. XBR0: Port I/O Crossbar Register R CP0AE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. Bit4: CP0E: Comparator0 Output Enable 0: CP0 unavailable at Port pin ...
Page 125
... Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the value of the register (not the pin) is read, modified, and written back to the SFR. C8051F330/1/2/3/4/5 R/W R/W ...
Page 126
... C8051F330/1/2/3/4/5 SFR Definition 14.3. P0: Port0 R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7–0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port pin when configured as digital input ...
Page 127
... Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input. 0: P1.n pin is logic low. 1: P1.n pin is logic high. C8051F330/1/2/3/4/5 R/W R/W R/W R/W Bit4 ...
Page 128
... C8051F330/1/2/3/4/5 SFR Definition 14.8. P1MDIN: Port1 Input Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an analog input. ...
Page 129
... P2.n pin is logic high. SFR Definition 14.12. P2MDOUT: Port2 Output Mode Bit7 Bit6 Bit5 Bits7–1: Unused. Read = 0000000b. Write = don’t care. Bit0: Output Configuration Bit for P2.0. 0: P2.0 Output is open-drain. 1: P2.0 Output is push-pull. C8051F330/1/2/3/4 Bit4 Bit3 Bit2 Bit1 (bit addressable ...
Page 130
... C8051F330/1/2/3/4/5 Table 14.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull Output High Voltage –10 mA, Port I/O push-pull 8 µA Output Low Voltage Input High Voltage Input Low Voltage Weak Pullup Off Input Leakage ...
Page 131
... SMBUS CONTROL LOGIC Arbitration Interrupt SCL Synchronization Request SCL Generation (Master Mode) SDA Control IRQ Generation Figure 15.1. SMBus Block Diagram C8051F330/1/2/3/4 Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL N Control Data Path SDA Control Control SMB0DAT FILTER N Rev. 1.7 SCL ...
Page 132
... C8051F330/1/2/3/4/5 15.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor. 3. System Management Bus Specification—Version 1.1, SBS Implementers Forum. ...
Page 133
... LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The win- ning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. C8051F330/1/2/3/4/5 R/W D7 D6-0 ...
Page 134
... C8051F330/1/2/3/4/5 15.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency ...
Page 135
... Timeout detection (SCL Low Timeout and/or Bus Free Timeout) • SDA setup and hold time extensions • Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in tion Register” on page 140 . C8051F330/1/2/3/4/5 Section “15.4.1. SMBus Configura- Rev. 1.7 139 ...
Page 136
... C8051F330/1/2/3/4/5 15.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins ...
Page 137
... SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 15.4). When a Free Timeout is detected, the interface will respond STOP was detected (an interrupt will be generated, and STO will be set). C8051F330/1/2/3/4/5 T SCL High Timeout High Minimum SDA Hold Time – ...
Page 138
... C8051F330/1/2/3/4/5 SFR Definition 15.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. ...
Page 139
... Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 15.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 15.4 for SMBus sta- tus decoding using the SMB0CN register. C8051F330/1/2/3/4/5 Rev. 1.7 143 ...
Page 140
... C8051F330/1/2/3/4/5 SFR Definition 15.2. SMB0CN: SMBus Control R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. Bit6: TXMODE: SMBus Transmit Mode Indicator. ...
Page 141
... ACK/NACK received. SI • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. C8051F330/1/2/3/4/5 Cleared by Hardware When: • A STOP is generated. • Arbitration is lost. • A START is detected. • Arbitration is lost. • SMB0DAT is not written before the start of an SMBus frame. • ...
Page 142
... C8051F330/1/2/3/4/5 15.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register ...
Page 143
... S SLA W A Data Byte Interrupt Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 15.5. Typical Master Transmitter Sequence Rev. 1.7 C8051F330/1/2/3/4/5 A Data Byte A P Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address 147 ...
Page 144
... C8051F330/1/2/3/4/5 15.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direc- tion bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to ‘ ...
Page 145
... Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. S SLA W Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 15.7. Typical Slave Receiver Sequence C8051F330/1/2/3/4/5 A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev ...
Page 146
... C8051F330/1/2/3/4/5 15.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set ...
Page 147
... ACK received. A master data byte was received; 1000 ACK requested. C8051F330/1/2/3/4/5 Typical Response Options Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT. End transfer with STOP. End transfer with STOP and start another transfer ...
Page 148
... C8051F330/1/2/3/4/5 Table 15.4. SMBus Status Decoding Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted error detected. An illegal STOP or bus error was 0101 detected while a Slave Transmis- sion was in progress. ...
Page 149
... UART0 interrupt (transmit complete or receive complete). Write to SBUF Stop Bit Start Tx Clock UART Baud Rate Generator Rx Clock Start Figure 16.1. UART0 Block Diagram C8051F330/1/2/3/4/5 ). Received data buffering allows SFR Bus TB8 SBUF SET (TX Shift CLR Zero Detector ...
Page 150
... C8051F330/1/2/3/4/5 16.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 16.2), which is not user- accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. ...
Page 151
... RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK START D0 D1 BIT SPACE BIT TIMES BIT SAMPLING Figure 16.4. 8-Bit UART Timing Diagram C8051F330/1/2/3/4/5 TX RS-232 RS-232 C8051Fxxx LEVEL RX XLTR ...
Page 152
... C8051F330/1/2/3/4/5 16.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg- ister PSW) for error detection, or used in multiprocessor communications ...
Page 153
... Master Slave Device Device Figure 16.6. UART Multi-Processor Mode Interconnect Diagram C8051F330/1/2/3/4/5 Slave Slave Device Device Rev. 1.7 V+ 157 ...
Page 154
... C8051F330/1/2/3/4/5 SFR Definition 16.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Bit6: UNUSED. Read = 1b. Write = don’ ...
Page 155
... This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmis- sion. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the con- tents of the receive latch. C8051F330/1/2/3/4/5 R/W R/W R/W ...
Page 156
... C8051F330/1/2/3/4/5 Table 16.1. Timer Settings for Standard Baud Rates Using the Internal 24.5 MHz Target Baud Rate Baud Rate % Error (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: – 1. SCA1 SCA0 and T1M bit definitions can be found Don’ ...
Page 157
... Notes: – 1. SCA1 SCA0 and T1M bit definitions can be found Don’t care. C8051F330/1/2/3/4/5 Oscillator Frequency: 22.1184 MHz Oscilla- Timer Clock SCA1–SCA0 tor Divide Source (pre-scale Factor select) 96 SYSCLK XX 192 ...
Page 158
... C8051F330/1/2/3/4/5 Table 16.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 0.00% 57600 ...
Page 159
... I/O pins can be used to select multiple slave devices in master mode. SPI0CKR Clock Divide SYSCLK Logic Transmit Data Buffer 7 6 Receive Data Buffer Write SPI0DAT SFR Bus Figure 17.1. SPI Block Diagram C8051F330/1/2/3/4/5 SFR Bus SPI0CFG SPI0CN SPI CONTROL LOGIC Data Path Pin Interface Control Control MOSI Tx Data SPI0DAT SCK ...
Page 160
... C8051F330/1/2/3/4/5 17.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 17.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operat- ing as a master and an input when SPI0 is operating as a slave ...
Page 161
... SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 17.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. C8051F330/1/2/3/4/5 Rev. 1.7 165 ...
Page 162
... C8051F330/1/2/3/4/5 Master Device 1 Figure 17.2. Multiple-Master Mode Connection Diagram Master Device Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Master Device GPIO Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection 166 NSS GPIO MISO MISO ...
Page 163
... The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. C8051F330/1/2/3/4/5 Rev. 1.7 167 ...
Page 164
... C8051F330/1/2/3/4/5 17.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock ...
Page 165
... SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. C8051F330/1/2/3/4/5 Bit 6 Bit 5 Bit 4 ...
Page 166
... C8051F330/1/2/3/4/5 SFR Definition 17.1. SPI0CFG: SPI0 Configuration R R/W R/W SPIBSY MSTEN CKPHA Bit7 Bit6 Bit5 Bit 7: SPIBSY: SPI Busy (read only). This bit is set to logic 1 when a SPI transfer is in progress (Master or slave Mode). Bit 6: MSTEN: Master Mode Enable. 0: Disable master mode. Operate in slave mode. ...
Page 167
... SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. Bit 0: SPIEN: SPI0 Enable. This bit enables/disables the SPI. 0: SPI disabled. 1: SPI enabled. C8051F330/1/2/3/4/5 R/W R/W R/W R TXBMT Bit4 ...
Page 168
... C8051F330/1/2/3/4/5 SFR Definition 17.3. SPI0CKR: SPI0 Clock Rate R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7 – 0: SCR7 – SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register ...
Page 169
... SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.9. SPI Master Timing (CKPHA = 1) C8051F330/1/2/3/4/5 T MCKL T T MIS MIH T MCKL T MIH Rev ...
Page 170
... C8051F330/1/2/3/4/5 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* T CKH T SIS MOSI T T SOH SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. ...
Page 171
... MOSI Valid to SCK Sample Edge SIS T SCK Sample Edge to MOSI Change SIH T SCK Shift Edge to MISO Change SOH Last SCK Edge to MISO Change T SLH (CKPHA = 1 ONLY) *Note equal to one period of the device system clock (SYSCLK). SYSCLK C8051F330/1/2/3/4/5 Min SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK — ...
Page 172
... C8051F330/1/2/3/4/5 176 Rev. 1.7 ...
Page 173
... As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled. C8051F330/1/2/3/4/5 Timer 2 Modes: 16-bit timer with auto-reload Two 8-bit timers with auto-reload Two 8-bit timers with auto-reload ” ...
Page 174
... C8051F330/1/2/3/4/5 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “14.1. Priority Crossbar Decoder” on page 125 pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system clock ...
Page 175
... TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is active as defined by bit IN0PL in register IT01CF (see Section “ for details on the external input signals /INT0 and /INT1). Pre-scaled Clock 0 SYSCLK 1 T0 Crossbar GATE0 IN0PL XOR /INT0 Figure 18.2. T0 Mode 2 Block Diagram C8051F330/1/2/3/4/5 9.3.2. External Interrupts CKCON TMOD IT01CF ...
Page 176
... C8051F330/1/2/3/4/5 18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock ...
Page 177
... IT0: Interrupt 0 Type Select. This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0 is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 9.11). 0: /INT0 is level triggered. 1: /INT0 is edge triggered. C8051F330/1/2/3/4/5 R/W R/W R/W R/W TR0 ...
Page 178
... C8051F330/1/2/3/4/5 SFR Definition 18.2. TMOD: Timer Mode R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 is active as defined by bit IN1PL in regis- ter IT01CF (see SFR Definition 9 ...
Page 179
... SCA0 0 0 System clock divided System clock divided System clock divided External clock divided by 8 Note: External clock divided synchronized with the system clock. C8051F330/1/2/3/4/5 R/W R/W R/W R/W T2ML T1M T0M SCA1 Bit4 Bit3 Bit2 Bit1 Prescaled Clock Rev. 1.7 ...
Page 180
... C8051F330/1/2/3/4/5 SFR Definition 18.4. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7 – 0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 18.5. TL1: Timer 1 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7 – ...
Page 181
... CKCON T2XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 18.4. Timer 2 16-Bit Mode Block Diagram C8051F330/1/2/3/4/5 To SMBus TL2 Overflow TCLK TR2 TMR2L TMR2H TMR2RLL TMR2RLH Reload Rev. 1.7 To ADC, SMBus TF2H Interrupt TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK 185 ...
Page 182
... C8051F330/1/2/3/4/5 18.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 18.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is always running when configured for 8-bit Mode ...
Page 183
... Timer 2 external clock selection is the system clock divided by 12. 1: Timer 2 external clock selection is the external clock divided by 8. Note that the external oscillator source divided synchronized with the system clock. C8051F330/1/2/3/4/5 R/W R/W R/W ...
Page 184
... C8051F330/1/2/3/4/5 SFR Definition 18.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7 – 0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition 18.10. TMR2RLH: Timer 2 Reload Register High Byte ...
Page 185
... TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L) overflow from 0xFF to 0x00. CKCON T3XCLK SYSCLK / External Clock / 8 1 SYSCLK 1 Figure 18.6. Timer 3 16-Bit Mode Block Diagram C8051F330/1/2/3/4 TCLK TR3 TMR3L TMR3H TMR3RLL TMR3RLH Reload Rev. 1.7 To ADC TF3H Interrupt TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK 189 ...
Page 186
... C8051F330/1/2/3/4/5 18.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 18.7. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control for TMR3H. TMR3L is always running when configured for 8-bit Mode ...
Page 187
... Timer 3 external clock selection is the system clock divided by 12. 1: Timer 3 external clock selection is the external clock divided by 8. Note that the external oscillator source divided synchronized with the system clock. C8051F330/1/2/3/4/5 R/W R/W R/W ...
Page 188
... C8051F330/1/2/3/4/5 SFR Definition 18.14. TMR3RLL: Timer 3 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7 – 0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3. SFR Definition 18.15. TMR3RLH: Timer 3 Reload Register High Byte ...
Page 189
... Important Note: The PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled . See Section 19.3 for details. Capture/Compare Figure 19.1. PCA Block Diagram C8051F330/1/2/3/4/5 Section “19.2. Capture/Compare SYSCLK/12 SYSCLK/4 Timer 0 Overflow PCA 16-Bit Counter/Timer ...
Page 190
... C8051F330/1/2/3/4/5 19.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. ...
Page 191
... PCA Counter/ Timer Overflow ECCF0 PCA Module 0 (CCF0) ECCF1 PCA Module 1 (CCF1) ECCF2 PCA Module 2 (CCF2) Figure 19.3. PCA Interrupt Block Diagram C8051F330/1/2/3/4/5 MAT TOG PWM ECCF Capture triggered by positive edge CEXn Capture triggered by negative edge on CEXn Capture triggered by transition CEXn ...
Page 192
... C8051F330/1/2/3/4/5 19.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun- ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge) ...
Page 193
... ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’. Write to 0 PCA0CPLn ENB Reset Write to PCA0CPHn ENB 1 PCA0CPMn Figure 19.5. PCA Software Timer Mode Diagram C8051F330/1/2/3/4 PCA0CPLn PCA0CPHn Enable 16-bit Comparator PCA PCA0L PCA0H Timebase Rev. 1.7 PCA Interrupt PCA0CN Match 1 197 ...
Page 194
... C8051F330/1/2/3/4/5 19.2.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High- Speed Output mode ...
Page 195
... ENB Reset PCA0CPMn Write PCA0CPHn ENB Figure 19.7. PCA Frequency Output Mode C8051F330/1/2/3/4/5 F PCA F = ---------------------------------------- - CEXn 2 PCA0CPHn E C PCA0CPLn 8-bit Adder C F Adder n Enable Toggle x 8-bit match Enable Comparator PCA Timebase PCA0L Rev. 1.7 PCA0CPHn TOGn 0 CEXn Crossbar Port I/O 1 199 ...
Page 196
... C8051F330/1/2/3/4/5 19.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. ...
Page 197
... PCA counter high byte; the Module 2 low byte holds the offset to be used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some PCA registers are restricted while the Watchdog Timer is enabled. C8051F330/1/2/3/4/5 ...
Page 198
... C8051F330/1/2/3/4/5 19.3.1. Watchdog Timer Operation While the WDT is enabled: • PCA counter is forced on. • Writes to PCA0L and PCA0H are not allowed. • PCA clock source bits (CPS2 – CPS0) are frozen. • PCA Idle control bit (CIDL) is frozen. • Module 2 is forced into software timer mode. ...
Page 199
... The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by 12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 19.6, this results in a WDT timeout interval of 256 PCA clock cycles, or 3072 system clock cycles. Table 19.4 lists some example time- out intervals for typical system clocks. C8051F330/1/2/3/4/5 ...
Page 200
... C8051F330/1/2/3/4/5 Table 19.4. Watchdog Timer Timeout Intervals System Clock (Hz) 24,500,000 24,500,000 24,500,000 18,432,000 18,432,000 18,432,000 11,059,200 11,059,200 11,059,200 3,062,500 3,062,500 3,062,500 32,000 32,000 32,000 Notes: 1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of 0x00 at the update time. 2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8. ...