C8051F410-TB Silicon Laboratories Inc, C8051F410-TB Datasheet
C8051F410-TB
Specifications of C8051F410-TB
Related parts for C8051F410-TB
C8051F410-TB Summary of contents
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... Timer 0 IDAC ADC Timer Timer 2 VREF - - Timer 3 VREG VOLTAGE CRC COMPARATORS LOW FREQUENCY INTERNAL OSCILLATOR HARDWARE smaRTClock HIGH-SPEED CONTROLLER CORE 8051 CPU (50 MIPS) DEBUG CIRCUITRY Copyright © 2008 by Silicon Laboratories C8051F410/1/2/3 Port 0 Port 1 Port 2 2368 B SRAM POR WDT C8051F41x ...
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... C8051F410/1/2 OTES 2 Rev. 1.1 ...
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... IDAC Output Scheduling................................................................................... 69 6.1.1. Update Output On-Demand ..................................................................... 69 6.1.2. Update Output Based on Timer Overflow ................................................ 70 6.1.3. Update Output Based on CNVSTR Edge................................................. 70 6.2. IDAC Output Mapping....................................................................................... 70 6.3. IDAC External Pin Connections ........................................................................ 73 7. Voltage Reference .................................................................................................. 77 8. Voltage Regulator (REG0)...................................................................................... 81 9. Comparators ......................................................................................................... 83 C8051F410/1/2/3 Rev. 1.1 3 ...
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... C8051F410/1/2/3 10. CIP-51 Microcontroller ........................................................................................... 93 10.1.Instruction Set................................................................................................... 94 10.1.1.Instruction and CPU Timing ..................................................................... 94 10.1.2.MOVX Instruction and Program Memory ................................................. 95 10.2.Register Descriptions ....................................................................................... 98 10.3.Power Management Modes............................................................................ 101 10.3.1.Idle Mode ............................................................................................... 102 10.3.2.Stop Mode.............................................................................................. 102 10.3.3.Suspend Mode ....................................................................................... 102 11. Memory Organization and SFRs ......................................................................... 103 11.1.Program Memory............................................................................................ 103 11.2.Data Memory .................................................................................................. 104 11.3.General Purpose Registers ............................................................................ 104 11 ...
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... Timer and Alarm Function......................................................... 185 20.3.1.Setting and Reading the smaRTClock Timer Value............................... 185 20.3.2.Setting a smaRTClock Alarm ................................................................. 186 20.4.Backup Regulator and RAM ........................................................................... 187 21. SMBus ................................................................................................................... 191 21.1.Supporting Documents ................................................................................... 192 21.2.SMBus Configuration...................................................................................... 192 21.3.SMBus Operation ........................................................................................... 192 21.3.1.Arbitration............................................................................................... 193 21.3.2.Clock Low Extension.............................................................................. 193 C8051F410/1/2/3 Rev. 1.1 5 ...
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... C8051F410/1/2/3 21.3.3.SCL Low Timeout................................................................................... 194 21.3.4.SCL High (SMBus Free) Timeout .......................................................... 194 21.4.Using the SMBus............................................................................................ 194 21.4.1.SMBus Configuration Register............................................................... 195 21.4.2.SMB0CN Control Register ..................................................................... 198 21.4.3.Data Register ......................................................................................... 201 21.5.SMBus Transfer Modes.................................................................................. 201 21.5.1.Master Transmitter Mode ....................................................................... 201 21.5.2.Master Receiver Mode ........................................................................... 202 21.5.3.Slave Receiver Mode ............................................................................. 203 21 ...
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... Pulse Width Modulator Mode......................................................... 256 25.2.6.16-Bit Pulse Width Modulator Mode....................................................... 257 25.3.Watchdog Timer Mode ................................................................................... 257 25.3.1.Watchdog Timer Operation .................................................................... 258 25.3.2.Watchdog Timer Usage ......................................................................... 259 25.4.Register Descriptions for PCA........................................................................ 261 26. C2 Interface ........................................................................................................... 265 26.1.C2 Interface Registers.................................................................................... 265 26.2.C2 Pin Sharing ............................................................................................... 267 C8051F410/1/2/3 Rev. 1.1 7 ...
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... C8051F410/1/2 OTES 8 Rev. 1.1 ...
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... List of Figures 1. System Overview Figure 1.1. C8051F410 Block Diagram .................................................................... 21 Figure 1.2. C8051F411 Block Diagram .................................................................... 22 Figure 1.3. C8051F412 Block Diagram .................................................................... 23 Figure 1.4. C8051F413 Block Diagram .................................................................... 24 Figure 1.5. Development/In-System Debug Diagram............................................... 26 Figure 1.6. Memory Map .......................................................................................... 27 Figure 1.7. 12-Bit ADC Block Diagram..................................................................... 29 Figure 1.8. IDAC Block Diagram .............................................................................. 30 Figure 1 ...
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... C8051F410/1/2/3 Figure 9.3. Comparator Hysteresis Plot ................................................................... 85 10. CIP-51 Microcontroller Figure 10.1. CIP-51 Block Diagram.......................................................................... 93 11. Memory Organization and SFRs Figure 11.1. Memory Map ...................................................................................... 103 12. Interrupt Handler 13. Prefetch Engine 14. Cyclic Redundancy Check Unit (CRC0) Figure 14.1. CRC0 Block Diagram ......................................................................... 121 Figure 14.2. Bit Reverse Register .......................................................................... 124 15 ...
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... Figure 25.7. PCA Frequency Output Mode ............................................................ 255 Figure 25.8. PCA 8-Bit PWM Mode Diagram ......................................................... 256 Figure 25.9. PCA 16-Bit PWM Mode...................................................................... 257 Figure 25.10. PCA Module 5 with Watchdog Timer Enabled ................................. 258 26. C2 Interface Figure 26.1. Typical C2 Pin Sharing....................................................................... 267 C8051F410/1/2/3 Rev. 1.1 11 ...
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... C8051F410/1/2 OTES 12 Rev. 1.1 ...
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... Cyclic Redundancy Check Unit (CRC0) Table 14.1. Example 16-bit CRC Outputs ............................................................. 122 Table 14.2. Example 32-bit CRC Outputs ............................................................. 124 15. Reset Sources Table 15.1.Reset Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16. Flash Memory Table 16.1. Flash Security Summary .................................................................... 138 Table 16.2.Flash Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 C8051F410/1/2 REF = 2 1 REF Rev ...
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... C8051F410/1/2/3 17. External RAM 18. Port Input/Output Table 18.1.Port I/O DC Electrical Characteristics 163 19. Oscillators Table 19.1.Oscillator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 175 20. smaRTClock (Real Time Clock) Table 20.1. smaRTClock Internal Registers .......................................................... 179 21. SMBus Table 21.1. SMBus Clock Source Selection .......................................................... 195 Table 21.2. Minimum SDA Setup and Hold Times ................................................ 196 Table 21 ...
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... SFR Definition 13.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . 119 SFR Definition 14.1. CRC0CN: CRC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 14.2. CRC0IN: CRC0 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SFR Definition 14.3. CRC0DAT: CRC0 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . 126 SFR Definition 14.4. CRC0FLIP: CRC0 Bit Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 C8051F410/1/2/3 Rev. 1.1 15 ...
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... C8051F410/1/2/3 SFR Definition 15.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . 130 SFR Definition 15.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SFR Definition 16.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 16.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 16.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 16 ...
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... SFR Definition 25.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 264 C2 Register Definition 26.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 C2 Register Definition 26.2. DEVICEID: C2 Device 265 C2 Register Definition 26.3. REVID: C2 Revision 266 C2 Register Definition 26.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 266 C2 Register Definition 26.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 266 C8051F410/1/2/3 Rev. 1.1 17 ...
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... C8051F410/1/2 OTES 18 Rev. 1.1 ...
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... Each device is specified for 2.0-to-2.75 V operation (supply voltage can 5.25 V using on-chip reg- ulator) over the industrial temperature range (–45 to +85 °C). The C8051F41x are available in 28-pin QFN (also referred to as MLP or MLF) or 32-pin LQFP packages. C8051F410/1/2/3 monitor, Watchdog Timer, and clock oscillator, the C8051F41x devices Rev. 1.1 ...
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... C8051F410/1/2/3 Table 1.1. Product Selection Guide C8051F410- 2368 C8051F411- 2368 C8051F412- 2368 C8051F413- 2368 20 ...
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... External XTAL1 Oscillator Clock XTAL2 Circuit Mult. 24.5 MHz 2% Oscillator 32 KHz 64B RAM XTAL3 XTAL4 Oscillator smaRTClock State Machine smaRTClock Block Figure 1.1. C8051F410 Block Diagram C8051F410/1/2/3 Port 0 Latch Port 1 Latch UART x16 Timer FLASH 0,1,2,3 0 256 B 5 SRAM PCA x6 / WDT ...
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... C8051F410/1/2/3 (to rest of chip) VREGIN VREG VDD (to smaRTClock Block) VRTC-BACKUP Battery Switch-Over Circuit (VDD >= VRTC-BACKUP) GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator Clock XTAL2 Circuit Mult. 24.5 MHz 2% Oscillator 32 KHz 64B RAM XTAL3 XTAL4 Oscillator smaRTClock State Machine smaRTClock Block Figure 1 ...
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... XTAL1 Oscillator Clock XTAL2 Circuit Mult. 24.5 MHz 2% Oscillator 32 KHz 64B RAM XTAL3 XTAL4 Oscillator smaRTClock State Machine smaRTClock Block Figure 1.3. C8051F412 Block Diagram C8051F410/1/2/3 Port 0 Latch Port 1 Latch UART x16 FLASH Timer 0 0,1,2,3 Reset 256 B 5 SRAM PCA x6 / WDT ...
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... C8051F410/1/2/3 (to rest of chip) VREGIN VREG VDD (to smaRTClock Block) VRTC-BACKUP Battery Switch-Over Circuit (VDD >= VRTC-BACKUP) GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator Clock XTAL2 Circuit Mult. 24.5 MHz 2% Oscillator 32 KHz 64B RAM XTAL3 XTAL4 Oscillator smaRTClock State Machine smaRTClock Block Figure 1 ...
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... A clock multiplier allows for operation MHz. The dedicated smaRTClock oscil- lator can be extremely useful in low power applications, allowing the system to maintain accurate time while the MCU is not powered, or its internal oscillator is suspended. The MCU can be reset or have its oscillator awakened using the smaRTClock alarm function. C8051F410/1/2/3 2 2/4 3 ...
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... All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them synchronized. The C8051F410DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F41x MCUs. The kit includes software with a developer's studio and debugger, a USB debug adapter, a target application board with the associated MCU installed, and the required cables and wall-mount power supply ...
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... Programmable in 512 Byte Sectors) 0x0000 ‘F412/3 RESERVED 0x4000 0x3FFF 16 kB Flash (In-System Programmable in 512 Byte Sectors) 0x0000 C8051F410/1/2/3 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE 0xFF Upper 128 RAM (Indirect Addressing Only) 0x80 0x7F (Direct and Indirect Addressing) 0x30 0x2F ...
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... C8051F410/1/2/3 1.4. Operating Modes The C8051F41x devices have four operating modes: Active (Normal), Idle, Suspend, and Stop. Active mode occurs during normal operation when the oscillator and peripherals are active. Idle mode halts the CPU while leaving the peripherals and internal clocks active. Suspend mode halts SYSCLK until a waken- ing event occurs, which also halts all peripherals using SYSCLK ...
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... The IDAC outputs can be merged onto a single port I/O pin for increased full-scale current output or increased resolution. IDAC updates can be performed on-demand, scheduled on a Timer overflow, or synchronized with an external signal. Figure 1.8 shows a block diagram of the IDAC circuitry. C8051F410/1/2/3 Configuration, Control, and Data Registers Start Conversion ...
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... C8051F410/1/2/3 Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR 12-bit Digital Input 12-bit Digital Input Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR Figure 1.8. IDAC Block Diagram 1.7. Programmable Comparators C8051F41x devices include two software-configurable voltage comparators with an input multiplexer. Each comparator offers programmable response time and hysteresis and two outputs that are optionally avail- able at the Port pins: a synchronous “ ...
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... The C8051F41x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. C8051F410/1/2/3 VDD Interrupt Logic ...
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... C8051F410/1/2/3 1.11. smaRTClock (Real Time Clock) C8051F41x devices include a smaRTClock Peripheral (Real Time Clock). The smaRTClock has a dedi- cated 32 kHz oscillator that can be configured for use with or without a crystal, a 47-bit smaRTClock timer with alarm, a backup supply regulator, and 64 bytes of backup SRAM. When the backup supply voltage ...
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... Figure 1.11. Port I/O Functional Block Diagram C8051F410/1/2/3 P0MASK, P0MATCH XBR0, XBR1, P1MASK, P1MATCH PnSKIP Registers Registers Priority PnMDOUT, PnMDIN Registers Decoder Digital Crossbar P0 8 I/O Cells P1 8 I/O Cells P2 8 I/O Cell P2.3–2.6 available on C8051F410/2 Rev. 1.1 P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 33 ...
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... C8051F410/1/2/3 1.13. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. The counter/timer is driven by a programmable timebase that ...
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... Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051F410/1/2/3 Conditions Min –55 – ...
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... C8051F410/1/2/3 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 50 MHz System Clock unless otherwise specified. Typical values are given at 25 °C Parameter 1 Supply Input Voltage (V ) REGIN Core Supply Voltage ( I/O Supply Voltage ( Backup Supply Voltage (V RTC-BACKUP Backup Supply Current ...
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... When using these numbers to estimate Idle for > 1 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example 2.8 mA – (25 MHz – 5 MHz) x 0.1 mA/MHz = 0.8 mA. DD C8051F410/1/2/3 Conditions Min kHz — ...
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... C8051F410/1/2/3 Table 3.1. Global DC Electrical Characteristics (Continued) –40 to +85 °C, 50 MHz System Clock unless otherwise specified. Typical values are given at 25 °C Parameter Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) 6 Core Supply Current ( 6,7 Supply Sensitivity (I ...
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... ADC0 Electrical Characteristics (VDD = 2.5 V, VREF = 2.2 V) ADC0 Electrical Characteristics (VDD = 2.1 V, VREF = 1.5 V) IDAC Electrical Characteristics Voltage Reference Electrical Characteristics Voltage Regulator Electrical Specifications Comparator Electrical Characteristics Reset Electrical Characteristics Flash Electrical Characteristics Port I/O DC Electrical Characteristics Oscillator Electrical Characteristics C8051F410/1/2/3 Rev. 1.1 Page # 134 ...
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... C8051F410/1/2 OTES 40 Rev. 1.1 ...
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... IDAC0 P0. IDAC1 P0 P0 C8051F410/1/2/3 Type Description Core Supply Voltage. I/O Supply Voltage. Ground. smaRTClock Backup Supply Voltage. On-Chip Voltage Regulator Input. D I/O Device Reset. Open-drain output of internal POR or V monitor. An external source can initiate a system reset by driving this pin low for at least 15 µ pullup to V recommended ...
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... C8051F410/1/2/3 Table 4.1. Pin Definitions for the C8051F41x (Continued) Pin Numbers Name ‘F410/2 ‘F411/3 P0. P0. P0. CNVSTR P0 P1. XTAL1 P1. XTAL2 P1 REF Type Description D I/O or Port 0.4. See Port I/O Section for a complete description UART TX Pin. See Port I/O Section for a complete descrip- D Out tion ...
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... P2 P2.3* 28 P2.4* 29 P2.5* 30 P2.6* 31 *Note: Available only on the C8051F410/2. C8051F410/1/2/3 Type Description D I/O or Port 1.7. See Port I/O Section for a complete description I/O or Port 2.0. See Port I/O Section for a complete description I/O or Port 2.1. See Port I/O Section for a complete description. ...
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... C8051F410/1/2 RST/C2CK RTC-BACKUP XTAL4 4 XTAL3 5 6 GND REGIN Figure 4.1. LQFP-32 Pinout Diagram (Top View) 44 C8051F410/2 Top View Rev. 1.1 24 P0.7 23 P0.6 / CNVSTR P0.3 19 P0.2 18 P0.1 / IDAC1 17 P0.0 / IDAC0 ...
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... RST / C2CK RTC-BACKUP XTAL4 3 XTAL3 4 GND REGIN Figure 4.2. QFN-28 Pinout Diagram (Top View) C8051F410/1/2/3 C8051F411/3 Top View GND Rev. 1 P0.3 18 P0.2 17 P0.1 / IDAC1 16 P0.0 / IDAC0 15 P1.7 45 ...
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... C8051F410/1/2/3 Figure 4.3. LQFP-32 Package Diagram Table 4.2. LQFP-32 Package Dimensions MIN TYP MAX — — 1.60 0.05 — 0.15 1.35 1.40 1.45 0.30 0.37 0.45 0.09 — 0.20 — 9.00 — — 7.00 — — 0.80 — — 9.00 — ...
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... Figure 4.4. LQFP-32 Recommended PCB Land Pattern Table 4.3. LQFP-32 PCB Land Pattern Dimensions Dimension Min C1 8. 0.40 Y1 1.25 Rev. 1.1 C8051F410/1/2/3 Max 8.50 8.50 0.80 BSC 0.50 1.35 47 ...
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... C8051F410/1/2/3 Figure 4.5. QFN-28 Package Drawing Table 4.4. QFN-28 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 A3 0.25 REF b 0.18 0.23 D 5.00 BSC. D2 2.90 3.15 e 0.50 BSC. E 5.00 BSC. E2 2.90 3.15 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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... A 3x3 array of 0.90mm openings on a 1.1mm pitch should be used for the center pad to assure the proper paste volume (67% Paste Coverage). Card Assembly 9. A No-Clean, Type-3 solder paste is recommended. 10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. C8051F410/1/2/3 Dimension Min X2 3.20 Y1 ...
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... C8051F410/1/2 OTES 50 Rev. 1.1 ...
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... PnMDIN (for n = 0,1,2) and write a ‘1’ in the corresponding Port Latch register Pn (for n = 0,1,2). To force the Crossbar to skip a Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See configuration details. C8051F410/1/2/3 ADC0CN ADC0TK Start ...
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... C8051F410/1/2/3 5.2. Temperature Sensor The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (V positive ADC input when the temperature sensor is selected by bits AD0MX4-0 in register ADC0MX. (Volts) 1.000 0.900 0.800 0.700 0.600 0.500 -50 Figure 5.2. Typical Temperature Sensor Transfer Function 5 ...
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... AD0TK is started immediately following the convert start signal. Conversions are started after the pro- grammed tracking time ends. After a conversion is complete, ADC0 tracks continuously until the next con- version is started. C8051F410/1/2/3 for timer configuration. for details on Port I/O configuration. Rev. 1.1 ...
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... C8051F410/1/2/3 Depending on the output connected to the ADC input, additional tracking time, more than is specified in Table 5.3 and Table 5.4, may be required after changing MUX settings. See the settling time requirements described in Section “5.3.6. Settling Time Requirements” on page 58 Convert Start Pre-Tracking ...
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... AD0INT Flag Post-Tracking or Dual-Tracking Modes (AD0TK = ‘00') Time ADC0 State Track AD0INT Flag Key F Equal to one period of FCLK. Each Sn is equal to one period of the SAR clock. Sn Figure 5.4. 12-Bit ADC Tracking Mode Example C8051F410/1/2/3 Pre-Tracking Mode ... S12 S13 F Convert ... S12 S13 Convert Rev ...
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... C8051F410/1/2/3 5.3.4. Burst Mode Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver- sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates sam- ples using an internal Burst Mode clock (approximately 25 MHz), then re-enters a low power state. Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a low power state within a single system clock cycle, even if the system clock is slow (e ...
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... Table 5.2. ADC0 Repeat Count Examples at Various Input Voltages Input Voltage Repeat Count = 4095/4096 0x3FFC REF V x 2048/4096 0x2000 REF V x 2047/4096 0x1FFC REF 0 0x0000 C8051F410/1/2/3 Left-Justified ADC0H:ADC0L (AD0LJST = 0) 0x0FFF 0x0800 0x07FF 0x0000 Repeat Count = 8 0x7FF8 0x4000 0x3FF8 0x0000 Rev. 1.1 x 4095/4096. REF (AD0LJST = 1) 0xFFF0 ...
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... C8051F410/1/2/3 5.3.6. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Figure 5.6 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling accuracy (SA) may be approximated by Equation 5 ...
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... Only applies to C8051F410/2; selection RESERVED on C8051F411/3 devices. C8051F410/1/2/3 R/W R/W R/W R/W AD0MX Bit4 Bit3 Bit2 Bit1 ADC0 Input Channel P0.0 P0.1 P0.2 P0.3 P0 ...
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... C8051F410/1/2/3 SFR Definition 5.2. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5 ...
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... ADC0 Data Word Low-Order Bits. Bits7-0: For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the ADC0 accumulated result. For AD0LJST = 1 (AD0RPT must be '00'): Bits 7-4 are the lower 4 bits of the 12-bit result. Bits 3-0 are 0000b. C8051F410/1/2/3 R/W R/W R/W R/W ...
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... C8051F410/1/2/3 SFR Definition 5.5. ADC0CN: ADC0 Control R/W R/W R/W AD0EN BURSTEN AD0INT AD0BUSY AD0WINT AD0LJST AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. ...
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... The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate when mea- sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0 Less-Than and ADC0 Greater-Than registers. C8051F410/1/2/3 R/W R/W R/W ...
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... C8051F410/1/2/3 SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: High byte of ADC0 Greater-Than Data Word. SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Greater-Than Data Word. ...
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... Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Less-Than Data Word. C8051F410/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W ...
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... C8051F410/1/2/3 5.4.1. Window Detector In Single-Ended Mode Figure 5.7 shows two example ADC0LTH:ADC0LTL = 0x0200 (512d) and ADC0GTH:ADC0GTL = 0x0100 (256d). The input voltage can range from ‘0’ (4095/4096) with respect to GND, and is represented by a 12-bit unsigned integer REF value. The repeat count is set to one. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0100 < ...
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... An additional 2 FCLK cycles are required to start and complete a conversion. 2. Additional tracking time may be required depending on the output impedance connected to the ADC input. 5.3.6. Settling Time Requirements See Section “ 3. Represents one standard deviation from the mean. 4. Includes ADC offset, gain, and linearity variations. C8051F410/1/2 REF Conditions ...
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... C8051F410/1/2/3 Table 5.4. ADC0 Electrical Characteristics ( 2 1.5 V (REFSL = 0), –40 to +85 °C unless otherwise specified. DD REF 25 ºC. Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Dynamic Performance (10 kHz sine-wave Single-ended input below Full Scale, 200 ksps) ...
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... IDAC data registers should be IDAnL followed by IDAnH . When the data word is left justified, the IDAC can be used in 8-bit mode by initializing IDAnL to the desired value (typically 0x00), and writing data only to IDA0H. C8051F410/1/2 IDAn 4 Rev ...
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... C8051F410/1/2/3 6.1.2. Update Output Based on Timer Overflow The IDAC output update can be scheduled on a Timer overflow. This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling rate, by eliminating the effects of variable interrupt latency and instruction execution on the timing of the IDAC output. When the IDAnCM bits (IDAnCN.[6:4]) are set to ‘ ...
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... Bits 7–0: IDA0 Data Word High-Order Bits. For IDA0RJST = 0: Bits 7-0 hold the most significant 8-bits of the 12-bit IDA0 Data Word. For IDA0RJST = 1: Bits 3-0 hold the most significant 4-bits of the 12-bit IDA0 Data Word. Bits 7-4 are 0000b. C8051F410/1/2/3 R/W R/W R R/W ...
Page 72
... C8051F410/1/2/3 SFR Definition 6.3. IDA0L: IDA0 Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: IDA0 Data Word Low-Order Bits. For IDA0RJST = 0: Bits 7-4 hold the least significant 4-bits of the 12-bit IDA0 Data Word. Bits 3–0 are 0000b. For IDA0RJST = 1: Bits 7– ...
Page 73
... IDAC output. When using the IDACs, the selected IDAC pin(s) should be skipped in the Crossbar by setting the corresponding PnSKIP bits to a ‘1’. Figure 6.3 shows the pin connections for IDA0 and IDA1. When both IDACs are enabled and IDAMRG is set to logic 1, the output of both IDACs is merged onto P0.0. C8051F410/1/2/3 R/W R/W R/W R/W ...
Page 74
... C8051F410/1/2/3 IDA0 IDA1 Figure 6.3. IDAC Pin Connections 74 IDA0EN 0 P0.0 1 IDA1EN IDAMRG Rev. 1.1 ...
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... Full Scale Output Current range 0.25 mA Full Scale Output Current Power Consumption 2 mA Full Scale Output Current 1 mA Full Scale Output Current Power Supply Current 0.5 mA Full Scale Output Current 0.25 mA Full Scale Output Current C8051F410/1/2/3 Conditions Min Typ — — — — — ...
Page 76
... C8051F410/1/2 OTES 76 Rev. 1.1 ...
Page 77
... REF0CN; see SFR Definition 7.1 for REF0CN register details. The electrical specifications for the voltage reference circuit are given in Table 7.1. Figure 7.1. Voltage Reference Functional Block Diagram C8051F410/1/2/3 power supply voltage (see Figure 7.1). The DD as the reference source, REFSL ...
Page 78
... C8051F410/1/2/3 Important Note About the V Pin: Port pin P1.2 is used as the external V REF the internal V . When using either an external voltage reference or the internal reference circuitry, P1.2 REF should be configured as an analog pin, and skipped by the Digital Crossbar. To configure P1 ana- log pin, clear Bit 2 in register P1MDIN to ‘0’ and set Bit 2 in register P1 to '1'. To configure the Crossbar to skip P1.2, set Bit 2 in register P1SKIP to ‘ ...
Page 79
... Power Supply Rejection External Reference (REFBE = 0) Input Voltage Range Sample Rate = 200 ksps; V Input Current Bias Generators ADC Bias Generator BIASE = ‘1’ Power Consumption (Internal) C8051F410/1/2/3 Conditions = 2 2 1.5 V: REF = 2 2.2 V: REF = 2 V REF Rev ...
Page 80
... C8051F410/1/2 OTES 80 Rev. 1.1 ...
Page 81
... V DD Figure 8.1. External Capacitors for Voltage Regulator Input/Output If the internal voltage regulator is not used, the 4.7 µF Figure 8.2. External Capacitors for Voltage Regulator Input/Output C8051F410/1/2/3 pin, powers the microcontroller core, and can be used µF 4.7 µF V 4.7 µF .1 µF ...
Page 82
... C8051F410/1/2/3 SFR Definition 8.1. REG0CN: Regulator Control R/W R/W R REGDIS Reserved — Bit7 Bit6 Bit5 Bit 7: REGDIS: Voltage Regulator Disable Bit. This bit disables/enables the Voltage Regulator. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit 6: RESERVED. Read = 0b. Must write 0b. Bit 5: UNUSED. Read = 0b. Write = don’t care. ...
Page 83
... P0.4 P0.3 P0.6 P0.5 P1.0 P0.7 P1.2 P1.1 P1.4 P1.3 P1.6 P1.5 P2.0 P1.7 P2.2 P2.1 P2.4 P2.3 P2.6 P2.5 P2.7 Figure 9.1. Comparator0 Functional Block Diagram C8051F410/1/2/3 ) VDD CP0 + + SET SET CLR CLR (SYNCHRONIZER) GND Reset Decision Tree CPT0MD CP0 - Rev ...
Page 84
... C8051F410/1/2/3 The Comparator output can be polled in software, used as an interrupt source, internal oscillator suspend awakening source and/or routed to a Port pin. When routed to a Port pin, the Comparator output is avail- able asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP or SUSPEND mode (with no system clock active) ...
Page 85
... Therefore recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. This Power Up Time is specified in Table 9.1 on page 92. C8051F410/1/2/3 OUT Negative Hysteresis Voltage ...
Page 86
... C8051F410/1/2/3 SFR Definition 9.1. CPT0CN: Comparator0 Control R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. Bit5: CP0RIF: Comparator0 Rising-Edge Flag. ...
Page 87
... These bits select which Port pin is used as the Comparator0 negative input. CMX0N3 CMX0N2 CMX0N1 CMX0N0 *Note: Available only on the C8051F410/2. Bits1–0: CMX0P3–CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P3 CMX0P2 CMX0P1 CMX0P0 ...
Page 88
... C8051F410/1/2/3 SFR Definition 9.3. CPT0MD: Comparator0 Mode Selection R/W R/W R/W RESERVED - CP0RIE Bit7 Bit6 Bit5 Bit7: RESERVED. Read = 0b. Must Write 0b. Bit6: UNUSED. Read = 0b. Write = don’t care. Bit5: CP0RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled. 1: Comparator rising-edge interrupt enabled. ...
Page 89
... These bits select which Port pin is used as the Comparator1 negative input. CMX1N3 CMX1N2 CMX1N1 CMX1N0 *Note: Available only on the C8051F410/2. Bits3–0: CMX1P3–CMX1P0: Comparator1 Positive Input MUX Select. These bits select which Port pin is used as the Comparator1 positive input. CMX1P3 CMX1P2 CMX1P1 CMX1P0 ...
Page 90
... C8051F410/1/2/3 SFR Definition 9.5. CPT1MD: Comparator1 Mode Selection R/W R/W R/W RESERVED - CP1RIE Bit7 Bit6 Bit5 Bit7: RESERVED. Read = 0b. Must Write 0b. Bit6: UNUSED. Read = 0b. Write = don’t care. Bit5: CP1RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled. 1: Comparator rising-edge interrupt enabled. ...
Page 91
... Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051F410/1/2/3 R/W R/W R/W CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit4 Bit3 Bit2 Rev ...
Page 92
... C8051F410/1/2/3 Table 9.1. Comparator Electrical Characteristics V = 2.0 V, –40 to +85 °C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 DD unless otherwise noted. Typical values are given at 25 ºC. Parameter Response Time: 1 Mode 0, Vcm = 1.5 V Response Time: 1 Mode 1, Vcm = 1.5 V Response Time: ...
Page 93
... PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE Figure 10.1. CIP-51 Block Diagram C8051F410/1/2/3 19 for more information about the available peripherals. The CIP-51 - Extended Interrupt Handler - Reset Input - Power Management Modes - Integrated Debug Logic DATA BUS B REGISTER TMP1 ...
Page 94
... C8051F410/1/2/3 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...
Page 95
... OR Register to A ORL A, direct OR direct byte to A Notes: 1. Assumes PFEN = 1 for all instruction timing. 2. MOVC instructions take clock cycles depending on instruction alignment and the FLRT setting (SFR Definition 16.3. FLSCL: Flash Scale). C8051F410/1/2/3 Description Arithmetic Operations Logical Operations Rev. 1.1 Section 1 ...
Page 96
... C8051F410/1/2/3 Table 10.1. CIP-51 Instruction Set Summary Mnemonic ORL A, @Ri OR indirect RAM to A ORL A, #data OR immediate to A ORL direct direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A ...
Page 97
... Decrement direct byte and jump if not zero NOP No operation Notes: 1. Assumes PFEN = 1 for all instruction timing. 2. MOVC instructions take clock cycles depending on instruction alignment and the FLRT setting (SFR Definition 16.3. FLSCL: Flash Scale). C8051F410/1/2/3 1 (Continued) Description Boolean Manipulation Program Branching Rev. 1.1 ...
Page 98
... C8051F410/1/2/3 Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. ...
Page 99
... SFR Definition 10.3. DPH: Data Pointer High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. C8051F410/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W ...
Page 100
... C8051F410/1/2/3 SFR Definition 10.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition borrow from (subtraction) the high order nibble ...
Page 101
... Turning off the oscil- lators lowers power consumption considerably; however a reset is required to restart the MCU. The C8051F41x devices feature a low-power SUSPEND mode, which stops the internal oscillator until a wakening event occurs. See Section “ C8051F410/1/2/3 R/W R/W R/W ACC ...
Page 102
... C8051F410/1/2/3 10.3.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode. ...
Page 103
... Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F410/1 implement 32k of this pro- gram memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x7DFF. Addresses above 0x7DFF are reserved on the 32 kB devices. The C8051F412/3 implement Flash from addresses 0x0000 to 0x3FFF ...
Page 104
... C8051F410/1/2/3 11.2. Data Memory The C8051F41x includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. ...
Page 105
... OSCICL CLKMUL RTC0ADR RTC0DAT SPI0DAT P0MDOUT P1MDOUT P2MDOUT CPT0CN CPT1MD TMR3L TL0 TL1 TH0 DPL DPH CRC0CN 2(A) 3(B) 4(C) Rev. 1.1 C8051F410/1/2/3 IDA1H EIP1 EIP2 EIE1 EIE2 P1SKIP P2SKIP P0MAT TMR2H PCA0CPM5 P1MAT ADC0LTH P0MASK ADC0L ADC0H P1MASK IDA1CN FLSCL ...
Page 106
... C8051F410/1/2/3 Table 11.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0H 0xBE ADC0 ADC0L 0xBD ADC0 ADC0GTH 0xC4 ADC0 Greater-Than Data High Byte ...
Page 107
... PCA0CPL0 0xFB PCA Capture 0 Low PCA0CPL1 0xE9 PCA Capture 1 Low PCA0CPL2 0xEB PCA Capture 2 Low PCA0CPL3 0xED PCA Capture 3 Low PCA0CPL4 0xFD PCA Capture 4 Low C8051F410/1/2/3 Description Rev. 1.1 Page 73 72 112 113 118 143 167 167 171 155 157 157 ...
Page 108
... C8051F410/1/2/3 Table 11.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address PCA0CPL5 0xD2 PCA Capture 5 Low PCA0CPM0 0xDA PCA Module 0 Mode PCA0CPM1 0xDB PCA Module 1 Mode PCA0CPM2 0xDC PCA Module 2 Mode PCA0CPM3 ...
Page 109
... Timer/Counter 3 Reload High TMR3RLL 0x92 Timer/Counter 3 Reload Low V Monitor Control VDM0CN 0xFF DD XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 C8051F410/1/2/3 Description Rev. 1.1 Page 243 243 243 247 248 248 248 248 130 153 154 109 ...
Page 110
... C8051F410/1/2/3 12. Interrupt Handler The C8051F41x family includes an extended interrupt system supporting a total of 18 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Each interrupt source has one or more associ- ated interrupt-pending flag(s) located in an SFR ...
Page 111
... ADC0 Window 0x004B Comparator ADC0 End of Conversion 0x0053 Programmable Counter 0x005B Array Comparator0 0x0063 Comparator1 0x006B Timer 3 Overflow 0x0073 Voltage Regulator Dropout 0x007B Port Match 0x0083 C8051F410/1/2/3 Priority Pending Flag Order Top None N/A N/A 0 IE0 (TCON. TF0 (TCON. IE1 (TCON. TF1 (TCON ...
Page 112
... C8051F410/1/2/3 12.4. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). ...
Page 113
... Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. Bit 0: PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. C8051F410/1/2/3 R/W R/W R/W R/W PS0 PT1 ...
Page 114
... C8051F410/1/2/3 SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ET3 ECP1 ECP0 Bit7 Bit6 Bit5 Bit 7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. ...
Page 115
... Bit 0: PSMB0: SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. C8051F410/1/2/3 R/W R/W R/W PPCA0 PADC0 PWADC0 ...
Page 116
... C8051F410/1/2/3 SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 R/W R/W R Bit7 Bit6 Bit5 Bits 7–2: UNUSED. Read = 000000b. Write = don’t care. Bit 1: EMAT: Enable Port Match Interrupt. This bit sets the masking of the Port Match interrupt. 0: Disable the Port Match interrupt. ...
Page 117
... The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. C8051F410/1/2/3 Section “24.1. Timer 0 and Timer 1” on page 231 IT1 ...
Page 118
... C8051F410/1/2/3 SFR Definition 12.7. IT01CF: INT0/INT1 Configuration R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 24.1. “TCON: Timer Control” on page 235 for INT0/1 edge- or level-sensitive interrupt selection. Bit 7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. ...
Page 119
... This bit allows block writes to Flash memory from software. 0: Each byte of a software Flash write is written individually. 1: Flash bytes are written in groups of two. Note: The prefetch engine should be disabled when changes to FLRT are made. See “16. Flash Memory” on page 135 C8051F410/1/2 ...
Page 120
... C8051F410/1/2 OTES 120 Rev. 1.1 ...
Page 121
... Step 2a. If the MSB of the CRC result is set, left-shift the CRC result, and then XOR the CRC result with the polynomial (0x1021). Step 2b. If the MSB of the CRC result is not set, left-shift the CRC result. Step 3. Repeat at Step 2a for the number of input bits (8). C8051F410/1/2/3 8 CRC0IN CRC Engine ...
Page 122
... C8051F410/1/2/3 For example, the 16-bit 'F41x CRC algorithm can be described by the following code: unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input) { unsigned char i; #define POLY 0x1021 // Create the CRC "dividend" for polynomial arithmetic (binary arithmetic // with no carries) CRC_acc = CRC_acc ^ (CRC_input << 8); ...
Page 123
... CRC value CRC_acc = CRC_acc >> Return the final remainder (CRC value) return CRC_acc; } The following table lists several input values and the associated outputs using the 32-bit 'F41x CRC algo- rithm (an initial value of 0xFFFFFFFF is used): C8051F410/1/2/3 Rev. 1.1 123 ...
Page 124
... C8051F410/1/2/3 Table 14.2. Example 32-bit CRC Outputs Input 0x63 0xAA, 0xBB, 0xCC 0x00, 0x00, 0xAA, 0xBB, 0xCC 14.3. Preparing for a CRC Calculation To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0 result may be initialized to one of two values: 0x00000000 or 0xFFFFFFFF ...
Page 125
... SFR Definition 14.2. CRC0IN: CRC0 Data Input R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: CRC0IN: CRC Data Input Each write to CRCIN results in the written data being computed into the existing CRC result. C8051F410/1/2/3 R/W W R/W R/W Bit4 Bit3 Bit2 Bit1 ...
Page 126
... C8051F410/1/2/3 SFR Definition 14.3. CRC0DAT: CRC0 Data Output R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: CRC0DAT: Indirect CRC Result Data Bits. Each operation performed on CRC0DAT targets the CRC result bits pointed to by CRC0PNT. SFR Definition 14.4. CRC0FLIP: CRC0 Bit Flip ...
Page 127
... RTC0RE Missing Clock Detector (one- shot) EN System Clock CIP-51 Microcontroller Core Extended Interrupt Handler Figure 15.1. Reset Sources C8051F410/1/2/3 for information on selecting and configuring details the use of the Watchdog Timer). VDD Power On Reset Supply Monitor + '0' - Enable PCA (Software Reset) WDT SWRSF ...
Page 128
... C8051F410/1/2/3 15.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until additional delay occurs before the device is released from reset; the delay decreases as the V RST ramp time increases (V ramp time is defined as how fast V ...
Page 129
... See Table 15.1 for complete electrical characteristics of the V Note: Software should take care not to inadvertently disable the V when writing to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should explicitly set PORSF to '1' to keep the V C8051F410/1/2/3 Monitor returns to a level above V DD RST dropped below the level required for data retention ...
Page 130
... C8051F410/1/2/3 SFR Definition 15.1. VDM0CN: V R/W R R/W VDMEN VDDSTAT VDMLVL Reserved Reserved Reserved Reserved Reserved 1v000000 Bit7 Bit6 Bit5 Bit7: VDMEN: V Monitor Enable. DD This bit turns the V monitor circuit on/off. The V DD until it is also selected as a reset source in register RSTSRC (SFR Definition 15.2). The V Monitor can be allowed to stabilize before it is selected as a reset source ...
Page 131
... Security Options” on page 137 • A Flash write or erase is attempted while the V The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by this reset. C8051F410/1/2/3 Section “25.3. Watchdog Timer Mode” Monitor is disabled. DD Rev. 1.1 ...
Page 132
... C8051F410/1/2/3 15.8. smaRTClock (Real Time Clock) Reset The smaRTClock can generate a system reset on two events: smaRTClock Oscillator Fail or smaRTClock Alarm. The smaRTClock Oscillator Fail event occurs when the smaRTClock Missing Clock Detector is enabled and the smaRTClock clock is below approximately 20 kHz. A smaRTClock alarm event occurs when the smaRTClock Alarm is enabled and the smaRTClock timer value matches the ALARMn registers. The smaRTClock can be configured as a reset source by writing a ‘ ...
Page 133
... DD 1: Read: Last reset was a power- Write: V monitor is a reset source. DD Bit0: PINRSF: HW Pin Reset Flag. 0: Source of last reset was not RST pin. 1: Source of last reset was RST pin. C8051F410/1/2/3 R/W R R/W R/W WDTRSF MCDRSF PORSF Bit4 Bit3 Bit2 Bit1 monitor reset ...
Page 134
... C8051F410/1/2/3 Table 15.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Typical values are given at 25 ºC. Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Impedance V Monitor Threshold ( RST-LOW V Monitor Threshold ( RST-HIGH ...
Page 135
... Step 4. Set the PSEE bit (register PSCTL). Step 5. Set the PSWE bit (register PSCTL). Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE and PSEE bits. Step 8. Re-enable interrupts. C8051F410/1/2/3 . Rev. 1.1 Section “26. C2 Monitor DD ...
Page 136
... C8051F410/1/2/3 16.1.3. Flash Write Procedure Bytes in Flash memory can be written one byte at a time groups of two. The FLBWE bit in register PFE0CN (SFR Definition 13.1) controls whether a single byte or a block of two bytes is written to Flash during a write operation. When FLBWE is cleared to ‘0’, the Flash will be written one byte at a time. When FLBWE is set to ‘ ...
Page 137
... Flash Security Lock Byte is unlocked when no other Flash pages are locked (all bits of the Lock Byte are ‘1’) and locked when any other Flash pages are locked (any bit of the Lock Byte is ‘0’). See the example below for an C8051F410. Security Lock Byte: 1’ ...
Page 138
... C8051F410/1/2/3 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Table 16.1 summarizes the Flash security features of the 'F41x devices ...
Page 139
... Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas to check are initialization code which enables other reset sources, such as the Missing Clock Detector or Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly verify this. C8051F410/1/2/3 and re-asserts /RST if VDD RST Rev. 1.1 ...
Page 140
... C8051F410/1/2/3 16.4.2. 16.4.2 PSWE Maintenance 7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one rou- tine in code that sets both PSWE and PSEE both to a '1' to erase Flash pages. ...
Page 141
... Flash by writing a non-0xA5 value to FLKEY from software. Read: When read, bits 1-0 indicate the current Flash lock state. 00: Flash is write/erase locked. 01: The first key code has been written (0xA5). 10: Flash is unlocked (writes/erases allowed). 11: Flash writes/erases disabled until the next reset. C8051F410/1/2 R ...
Page 142
... C8051F410/1/2/3 16.5. Flash Read Timing On reset, the C8051F41x Flash read timing is configured for operation with system clocks MHz. If the system clock will not be increased above 25 MHz, then the Flash timing registers may be left at their reset value. For every Flash read or fetch, the system provides an internal Flash read strobe to the Flash memory. The Flash read strobe lasts for one or two system clock cycles, based on FLRT (FLSCL ...
Page 143
... greater Endurance DD Erase Cycle Time FLSCL.3–0 written to '0000' Write Cycle Time FLSCL.3–0 written to '0000' Read Cycle Time V Write/Erase Operations DD *Note: 512 bytes at addresses 0x7E00 to 0x7FFF are reserved. C8051F410/1/2/3 R R/W R/W - PERIOD Bit4 Bit3 Bit2 + PERIOD 5ns ...
Page 144
... C8051F410/1/2 OTES 144 Rev. 1.1 ...
Page 145
... MOVX command, effectively selecting a 256-byte page of RAM. Since the upper (unused) bits of the register are always zero, the PGSEL determines which page of XRAM is accessed. For Example: If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed. C8051F410/1/2/3 Section “16. Flash Memory” on page 135 R/W R/W ...
Page 146
... C8051F410/1/2 OTES 146 Rev. 1.1 ...
Page 147
... Port I/ and P2 should not be IO P0MASK, P0MATCH XBR0, XBR1, P1MASK, P1MATCH PnSKIP Registers Registers Priority PnMDOUT, PnMDIN Registers Decoder Digital Crossbar P0 8 I/O Cells P1 8 I/O Cells P2 8 I/O Cell P2.3–2.6 available on C8051F410/2 Rev. 1.1 P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 147 ...
Page 148
... C8051F410/1/2/3 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 18.2. Port I/O Cell Block Diagram 148 VIO VIO (WEAK) GND Rev. 1.1 PORT PAD ...
Page 149
... P0 SF Signa PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A /SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI P0SKIP[0:7] Figure 18.3. Crossbar Priority Decoder with No Pins Skipped C8051F410/1/2/3 P1 cnvstr vre (*4-W ire SPI Only P1SKIP[0:7] Rev. 1 ...
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... C8051F410/1/2 Signa PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A /SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI P0SKIP[0:7] Port pin potentially assignable to peripheral SF Signa ls Special Function Signals are not assigned by the crossbar. W hen these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins ...
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... Overdrive Mode is selected and the port pin does not require any additional overdrive current. Pins configured to High-Impedance Overdrive Mode consume slightly more power from V ured to Normal Overdrive Mode. Note that Port 1 and Port 2 pins cannot be overdriven above V have the same behavior Normal Mode. C8051F410/1/2/3 . Figure 18.5 shows the IO (when ...
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... C8051F410/1/2 P0.x I Vtest pin I/O Cell + - Figure 18.5. Port 0 Input Overdrive Current Range The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD- OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic ...
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... SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. Note that the SPI can be assigned either GPIO pins. Bit0: URT0E: UART I/O Output Enable 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.4 and P0.5. C8051F410/1/2/3 R/W R/W R/W R/W CP0E ...
Page 154
... C8051F410/1/2/3 SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input). 1: Weak Pullups disabled. Bit6: XBARE: Crossbar Enable ...
Page 155
... Corresponding P0.n pin is configured as an analog input. In order for the P0.n pin analog input mode, there MUST be a '1' in the Port Latch register corresponding to that pin. 1: Corresponding P0.n pin is not configured as an analog input. C8051F410/1/2/3 166 for more information. R/W R/W R/W P0 ...
Page 156
... C8051F410/1/2/3 SFR Definition 18.5. P0MDOUT: Port0 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT) ...
Page 157
... Port pins configured to Normal Overdrive Mode require approximately 150 µA of input overdrive cur- rent when the voltage at the pin reaches V 0: Corresponding P0.n pin is configured to Normal Overdrive Mode. 1: Corresponding P0.n pin is configured to High-Impedance Overdrive Mode. C8051F410/1/2/3 R/W R/W R/W R/W ...
Page 158
... C8051F410/1/2/3 SFR Definition 18.10. P1: Port1 R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input ...
Page 159
... These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (V lator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. C8051F410/1/2/3 R/W R/W R/W R/W ...
Page 160
... C8051F410/1/2/3 SFR Definition 18.14. P1MAT: Port1 Match R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: P1MAT[7:0]: Port1 Match Value. These bits control the value that unmasked P0 Port pins are compared against. A Port Match event is generated if (P1 & P1MASK) does not equal (P1MAT & P1MASK). ...
Page 161
... Corresponding P2.n pin is configured as an analog input. In order for the P2.n pin analog input mode, there MUST be a '1' in the Port Latch register corresponding to that pin. 1: Corresponding P2.n pin is not configured as an analog input. C8051F410/1/2/3 R/W R/W R/W R/W P2 ...
Page 162
... C8051F410/1/2/3 SFR Definition 18.18. P2MDOUT: Port2 Output Mode Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in regis- ter P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. SFR Definition 18.19. P2SKIP: Port2 Skip ...
Page 163
... µ 8 Output Low Voltage µ 8 Input High Voltage Input Low Voltage Input Leakage Current Weak Pullup Off Weak Pullup Impedance C8051F410/1/2/3 Conditions Min V – 0 – — — — — 0.7 IO — — — Rev. 1.1 Typ Max Units — ...
Page 164
... C8051F410/1/2 OTES 164 Rev. 1.1 ...
Page 165
... Electrical specifications for the precision internal oscillator are given in Table 19.1 on page 175. Note that the system clock may be derived from the programmed internal oscillator divided 16, 32, 64, or 128 as defined by the IFCN bits in register OSCICN. The divide value defaults to 128 following a reset. C8051F410/1/2/3 OSCICN EN ...
Page 166
... C8051F410/1/2/3 19.1.1. Internal Oscillator Suspend Mode When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys- tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped until one of the following events occur: • ...
Page 167
... Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6–0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. On C8051F41x devices, the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz. C8051F410/1/2 R/W R IFCN2 IFCN1 ...
Page 168
... C8051F410/1/2/3 19.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 19. ...
Page 169
... Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. C8051F410/1/2/3 XTAL1 XTAL2 Rev ...
Page 170
... C8051F410/1/2/3 19.2.3. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 19.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter- mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation ...
Page 171
... R = Pullup resistor value in k C Mode (Circuit from Figure 19.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired where frequency of clock in MHz C = capacitor value the XTAL2 pin Power Supply on MCU in volts DD C8051F410/1/2/3 R/W R/W R/W R/W XFCN2 XFCN1 Bit4 Bit3 Bit2 Bit1 RC (XOSCMD = 10x) f ...
Page 172
... C8051F410/1/2/3 19.3. Clock Multiplier The Clock Multiplier generates an output clock which is 4 times the input clock frequency scaled by a pro- grammable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7. The Clock Multiplier’s input can be selected from the external oscillator, or the internal or external oscillators divided by 2. This produces three possible base outputs which can be scaled by a programmable factor: Internal Oscillator x 2, External Oscillator External Oscillator x 4 ...
Page 173
... Clock Multiplier Output scaled by a factor of 2/7*. *Note: The Clock Multiplier Output duty cycle is not 50% for these settings. Bits1–0: MULSEL: Clock Multiplier Input Select These bits select the clock supplied to the Clock Multiplier. MULSEL C8051F410/1/2/3 R/W R/W R/W R/W MULDIV Bit4 Bit3 Bit2 ...
Page 174
... C8051F410/1/2/3 19.4. System Clock Selection The internal oscillator requires little start-up time and may be selected as the system clock immediately fol- lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ- ically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘ ...
Page 175
... Table 19.1. Oscillator Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Internal Oscillator Frequency Reset Frequency Internal Oscillator Supply OSCICN Current (from Minimum Clock Multiplier Input °C Frequency (FCM ) min C8051F410/1/2/3 Conditions Min Typ 24 24.5 — 400 — 1.6 Rev. 1.1 Max Units 25 MHz — ...
Page 176
... C8051F410/1/2 OTES 176 Rev. 1.1 ...
Page 177
... XTAL4 smaRTClock Oscillator smaRTClock State Machine 64B Backup RAM Backup Switchover Regulator Logic V RTC-BACKUP Figure 20.1. smaRTClock Block Diagram C8051F410/1/2/3 is greater than V RTC-BACKUP XTAL3 smaRTClock 47-Bit smaRTClock Timer Interrupt Internal Interface Registers Registers ...
Page 178
... C8051F410/1/2/3 20.1. smaRTClock Interface The smaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These inter- face registers are located on the CIP-51’s SFR map and provide access to the smaRTClock internal regis- ters listed in Table 20.1. The smaRTClock internal registers can only be accessed indirectly through the smaRTClock Interface ...
Page 179
... Backup RAM Indirect Address Register 0x0F RAMDATA smaRTClock Backup RAM Indirect Data Register C8051F410/1/2/3 Register Name Six Registers used for setting the 47-bit smaRTClock timer or reading its current value. The LSB of CAPTURE0 is not used. Controls the operation of the smaRTClock State Machine. ...
Page 180
... C8051F410/1/2/3 SFR Definition 20.1. RTC0KEY: smaRTClock Lock and Key R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: RTC0STATE. smaRTClock State Bits Read: 0x00: smaRTClock Interface is locked. 0x01: smaRTClock Interface is locked. First key code (0xA5) has been written, waiting for second key code. ...
Page 181
... Note: The RTC0ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMn internal register. C8051F410/1/2/3 R/W R/W R/W R/W RTC0ADDR Bit4 Bit3 Bit2 Bit1 > RTC-BACKUP DD CAPTURE0 ...
Page 182
... C8051F410/1/2/3 SFR Definition 20.3. RTC0DAT: smaRTClock Data R/W R/W R/W Bit7 Bit6 Bit5 Note: Software should avoid read modify write instructions when writing values to RTC0DAT. Bits 7–0: RTC0DAT. smaRTClock Data Bits Holds data transferred to/from the internal smaRTClock register selected by RTC0ADR. ...
Page 183
... Awakening the internal oscillator from Suspend Mode. 2. smaRTClock Interrupt (If the smaRTClock Interrupt is enabled). 3. MCU reset (If smaRTClock is enabled as a reset source). Note: The smaRTClock Missing Clock Detector should be disabled when making changes to the oscillator settings in RTC0XCN. C8051F410/1/2/3 Rev. 1.1 183 ...
Page 184
... C8051F410/1/2/3 Internal Register Definition 20.4. RTC0CN: smaRTClock Control R/W R/W R/W RTC0EN MCLKEN OSCFAIL RTC0TR RTC0AEN Bit7 Bit6 Bit5 Note: This register is not an SFR. It can only be accessed indirectly through RTC0ADR and RTC0DAT. Bit 7: RTC0EN: smaRTClock Enable Bit. 0: smaRTClock bias and crystal oscillator disabled. smaRTClock is powered from V 1: smaRTClock bias and crystal oscillator enabled ...
Page 185
... Step 1. Write the desired 47-bit set value to the CAPTUREn registers (the LSB of CAPTURE0 is not used). Step 2. Write ‘1’ to RTC0SET. This will transfer the contents of the CAPTUREn registers to the timer. Step 3. Operation is complete when RTC0SET is cleared to ‘0’ by hardware. C8051F410/1/2 CLKVLD ...
Page 186
... C8051F410/1/2/3 The following steps can be used to read the current timer value: Step 1. Write ‘1’ to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn registers (the LSB of the smaRTClock timer will be found in CAPTURE0.1). Step 2. Poll RTC0CAP until it is cleared to ‘0’ by hardware. ...
Page 187
... Note: This register is not an SFR. It can only be accessed indirectly through RTC0ADR and RTC0DAT. Bit 7: RAMADDR: smaRTClock Battery Backup RAM Address Bits These bits select the smaRTClock Backup RAM byte that is targeted by RAMDATA. This address auto-increments after each read or write of RAMDATA. C8051F410/1/2/3 R/W R/W R/W R/W ...
Page 188
... C8051F410/1/2/3 Internal Register Definition 20.9. RAMDATA: smaRTClock Backup RAM Data R/W R/W R/W Bit7 Bit6 Bit5 Note: This register is not an SFR. It can only be accessed indirectly through RTC0ADR and RTC0DAT. Bit 7: RAMDATA: smaRTClock Battery Backup RAM Data Bits. These bits provide read and write access to the smaRTClock Backup RAM byte that is selected by RAMADDR ...
Page 189
... RTC0DAT = 0xA5; // write 0xA5 to every RAM address while ((RTC0ADR & 0x80) == 0x80);// poll on the BUSY bit } // Read from the entire smaRTClock RAM RTC0ADR = 0x0E;// address the RAMADDR register C8051F410/1/2/3 // poll on the BUSY bit Rev. 1.1 189 ...
Page 190
... C8051F410/1/2/3 RTC0DAT = 0x00;// write the address of 0x00 to RAMADDR while ((RTC0ADR & 0x80) == 0x80); RTC0ADR = 0x0F; // address the RAMDATA register for (addr = 0; addr < 64; addr++) { RTC0ADR |= 0x80; // initiate a read of the RAMDATA register while ((RTC0ADR & 0x80) == 0x80); // poll on the BUSY bit RAM_data[addr] = RTC0DAT; // copy the data from the entire RAM ...
Page 191
... SMBUS CONTROL LOGIC Arbitration Interrupt SCL Synchronization Request SCL Generation (Master Mode) SDA Control IRQ Generation Figure 21.1. SMBus Block Diagram C8051F410/1/2 Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL N Control Data Path SDA Control Control SMB0DAT FILTER N Rev. 1.1 SCL ...
Page 192
... C8051F410/1/2/3 21.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C Manual (AN10216-01), Philips Semiconductor. 2. System Management Bus Specification -- Version 2, SBS Implementers Forum. 21.2. SMBus Configuration Figure 21.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between 3.0 V and 5.0 V ...
Page 193
... A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. C8051F410/1/2/3 R/W D7 ...
Page 194
... C8051F410/1/2/3 21.3.3. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than “ ...
Page 195
... Equation 21.1. When the interface is operating as a master (and SCL is not driven or extended by any other devices on the bus), the typical SMBus bit rate is approximated by Equation 21.2. BitRate Equation 21.2. Typical SMBus Bit Rate C8051F410/1/2/3 Section “21.4.1. SMBus Configura- SMBus Clock Source 0 ...
Page 196
... C8051F410/1/2/3 Figure 21.4 shows the typical SCL generation described by Equation 21.2. Notice that T twice as large The actual SCL output may vary due to other devices on the bus (SCL may be LOW extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 21 ...
Page 197
... These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The selected device should be configured according to Equation 21.1. SMBCS1 SMBCS0 C8051F410/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 SMBus Clock Source Timer 0 Overflow Timer 1 Overflow ...
Page 198
... C8051F410/1/2/3 21.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 21.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive modes, respectively ...
Page 199
... An "acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in Receiver Mode). Bit0: SI: SMBus Interrupt Flag. This bit is set by hardware under the conditions listed in Table 21.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. C8051F410/1/2/3 R R/W STO ...
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... C8051F410/1/2/3 Table 21.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: • A START is generated. MASTER • START is generated. • SMB0DAT is written before the start of an TXMODE SMBus frame. • A START followed by an address byte is STA received. • A STOP is detected while addressed as a STO slave ...