C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet
C8051F060-TB
Specifications of C8051F060-TB
Related parts for C8051F060-TB
C8051F060-TB Summary of contents
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... Flash; In-system programmable in 512-byte sectors - External 64 kB data memory interface with multi- plexed and non-multiplexed modes (C8051F060/2/ 4/6) Digital Peripherals - 59 general purpose I/O pins (C8051F060/2/4/ general purpose I/O pins (C8051F061/3/5/7) - Bosch Controller Area Network (CAN 2.0B - C8051F060/1/2/3) - Hardware SMBus™ (I2C™ Compatible), SPI™, and ...
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... C8051F060/1/2/3/4/5/6/7 2 Rev. 1.2 ...
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... XRAM Addressing and Setup ........................................................................... 76 6.4. Instruction Execution in Mode 0........................................................................ 77 6.5. Instruction Execution in Mode 1........................................................................ 78 6.6. Interrupt Sources .............................................................................................. 79 6.7. Data Buffer Overflow Warnings and Errors....................................................... 79 7. 10-Bit ADC (ADC2, C8051F060/1/2/3).................................................................... 87 7.1. Analog Multiplexer ............................................................................................ 88 7.2. Modes of Operation .......................................................................................... 89 7.2.1. Starting a Conversion............................................................................... 89 7.2.2. Tracking Modes........................................................................................ 90 7 ...
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... Programmable Window Detector ...................................................................... 97 7.3.1. Window Detector In Single-Ended Mode ................................................. 99 7.3.2. Window Detector In Differential Mode.................................................... 100 8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) .................... 103 8.1. DAC Output Scheduling.................................................................................. 104 8.1.1. Update Output On-Demand ................................................................... 104 8.1.2. Update Output Based on Timer Overflow .............................................. 104 8 ...
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... MOVX with Bank Select: EMI0CF[4:2] = ‘010’....................... 201 18. Port Input/Output.................................................................................................. 203 18.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 205 18.1.1.Crossbar Pin Assignment and Allocation ............................................... 205 18.1.2.Configuring the Output Modes of the Port Pins...................................... 206 18.1.3.Configuring Port Pins as Digital Inputs................................................... 207 18.1.4.Weak Pull-ups ........................................................................................ 207 C8051F060/1/2/3/4/5/6/7 Rev. 1.2 5 ...
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... Output Modes of the Port Pins...................................... 219 18.2.3.Configuring Port Pins as Digital Inputs................................................... 219 18.2.4.Weak Pull-ups ........................................................................................ 219 18.2.5.External Memory Interface ..................................................................... 220 19. Controller Area Network (CAN0, C8051F060/1/2/3) ........................................... 225 19.1.Bosch CAN Controller Operation.................................................................... 227 19.2.CAN Registers................................................................................................ 228 19.2.1.CAN Controller Protocol Registers......................................................... 228 19.2.2.Message Object Interface Registers ...................................................... 228 19 ...
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... Output Mode ........................................................................ 309 25.2.5.8-Bit Pulse Width Modulator Mode......................................................... 310 25.2.6.16-Bit Pulse Width Modulator Mode....................................................... 311 25.3.Register Descriptions for PCA0...................................................................... 312 26. JTAG (IEEE 1149.1) .............................................................................................. 317 26.1.Boundary Scan ............................................................................................... 318 26.1.1.EXTEST Instruction................................................................................ 321 26.1.2.SAMPLE Instruction ............................................................................... 321 26.1.3.BYPASS Instruction ............................................................................... 321 26.1.4.IDCODE Instruction................................................................................ 321 C8051F060/1/2/3/4/5/6/7 Rev. 1.2 7 ...
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... C8051F060/1/2/3/4/5/6/7 26.2.Flash Programming Commands..................................................................... 322 26.3.Debug Support ............................................................................................... 325 27. Document Change List ........................................................................................ 327 27.1.Revision 1.1 to Revision 1.2 ........................................................................... 327 8 Rev. 1.2 ...
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... List of Figures 1. System Overview.................................................................................................... 19 Figure 1.1. C8051F060 / C8051F062 Block Diagram .............................................. 21 Figure 1.2. C8051F061 / C8051F063 Block Diagram .............................................. 22 Figure 1.3. C8051F064 / C8051F066 Block Diagram .............................................. 23 Figure 1.4. C8051F065 / C8051F067 Block Diagram .............................................. 24 Figure 1.5. Comparison of Peak MCU Execution Speeds ....................................... 25 Figure 1.6. On-Board Clock and Reset .................................................................... 26 Figure 1 ...
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... Figure 6.15. DMA0CTL: DMA0 Repeat Counter Limit LSB Register ....................... 85 Figure 6.16. DMA0CSH: DMA0 Repeat Counter MSB Register .............................. 85 Figure 6.17. DMA0CSL: DMA0 Repeat Counter LSB Register................................ 85 7. 10-Bit ADC (ADC2, C8051F060/1/2/3).................................................................... 87 Figure 7.1. ADC2 Functional Block Diagram............................................................ 87 Figure 7.2. Temperature Sensor Transfer Function ................................................. 89 Figure 7 ...
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... Figure 7.17. ADC Window Compare Example: Right-Justified Differential Data.... 100 Figure 7.18. ADC Window Compare Example: Left-Justified Differential Data ...... 100 8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) .................... 103 Figure 8.1. DAC Functional Block Diagram............................................................ 103 Figure 8.2. DAC0H: DAC0 High Byte Register ...................................................... 105 Figure 8 ...
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... Figure 15.4. CLKSEL: Oscillator Clock Selection Register .................................... 173 Figure 15.5. OSCXCN: External Oscillator Control Register.................................. 174 16. Flash Memory ....................................................................................................... 177 Figure 16.1. C8051F060/1/2/3/4/5 Flash Program Memory Map and Security Bytes .. 180 Figure 16.2. C8051F066/7 Flash Program Memory Map and Security Bytes ........ 181 Figure 16 ...
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... Figure 18.24. P6MDOUT: Port6 Output Mode Register ......................................... 223 Figure 18.25. P7: Port7 Data Register ................................................................... 224 Figure 18.26. P7MDOUT: Port7 Output Mode Register ......................................... 224 19. Controller Area Network (CAN0, C8051F060/1/2/3) ........................................... 225 Figure 19.1. CAN Controller Diagram..................................................................... 226 Figure 19.2. Typical CAN Bus Configuration.......................................................... 226 Figure 19 ...
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... C8051F060/1/2/3/4/5/6/7 Figure 21.1. SPI Block Diagram ............................................................................. 251 Figure 21.2. Multiple-Master Mode Connection Diagram ....................................... 254 Figure 21.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram 254 Figure 21.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 254 Figure 21.5. Master Mode Data/Clock Timing ........................................................ 256 Figure 21 ...
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... Figure 26.1. IR: JTAG Instruction Register............................................................. 317 Figure 26.2. DEVICEID: JTAG Device ID Register ................................................ 321 Figure 26.3. FLASHCON: JTAG Flash Control Register........................................ 323 Figure 26.4. FLASHDAT: JTAG Flash Data Register............................................. 324 Figure 26.5. FLASHADR: JTAG Flash Address Register....................................... 324 27. Document Change List ........................................................................................ 327 C8051F060/1/2/3/4/5/6/7 Rev. 1.2 15 ...
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... C8051F060/1/2/3/4/5/6/7 16 Rev. 1.2 ...
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... Direct Memory Access Interface (DMA0) ............................................................ 75 Table 6.1.DMA0 Instruction Set .............................................................................. 76 7. 10-Bit ADC (ADC2, C8051F060/1/2/3) ................................................................... 87 Table 7.1.ADC2 Electrical Characteristics ............................................................ 101 8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) ................... 103 Table 8.1.DAC Electrical Characteristics .............................................................. 109 9. Voltage Reference 2 (C8051F060/2) ................................................................... 111 Table 9.1.Voltage Reference Electrical Characteristics ........................................ 112 10 ...
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... Programmable Counter Array ............................................................................ 303 Table 25.1.PCA Timebase Input Options .............................................................. 304 Table 25.2.PCA0CPM Register Settings for PCA Capture/Compare Modules ..... 305 26. JTAG (IEEE 1149.1) ............................................................................................. 317 Table 26.1.Boundary Data Register Bit Definitions (C8051F060/2/4/6) ................ 318 Table 26.2.Boundary Data Register Bit Definitions (C8051F061/3/5/7) ................ 320 27. Document Change List ....................................................................................... 327 18 ...
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... System Overview The C8051F06x family of devices are fully integrated mixed-signal System-on-a-Chip MCUs with 59 digital I/O pins (C8051F060/2/4/ digital I/O pins (C8051F061/3/5/7), and two integrated 16-bit 1 Msps ADCs. Highlighted features are listed below; refer to Table 1.1 for specific product feature selection. • ...
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... C8051F060/1/2/3/4/5/6/7 Table 1.1. Product Selection Guide C8051F060 4352 C8051F061 4352 - C8051F062 4352 C8051F063 4352 - C8051F064 4352 C8051F065 4352 - C8051F066 4352 C8051F067 4352 - 20 ±0.75 8 ±0.75 8 ±1.5 8 ...
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... A AV+ + AGND VREF1 VRGND ADC1 AIN1 1Msps D AIN1G (16-Bit VBGAP A CNVSTR 1 1 Figure 1.1. C8051F060 / C8051F062 Block Diagram C8051F060/1/2/3/4/5/6/7 UART0 8 UART1 0 SFR Bus SMBus SPI Bus 5 PCA 1 Timers 0, 1, 2,3,4 64kbyte P0, P1, P2, FLASH P3 Latches C 32X136 CAN CANRAM o 2.0B r 256 byte ...
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... C8051F060/1/2/3/4/5/6/7 VDD VDD Digital Power VDD DGND DGND Analog Power DGND AV+ AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD Monitor WDT MONEN External Oscillator XTAL1 XTAL2 Circuit System Clock Trimmed Internal Oscillator VREF VREF VREF2 DAC0 ...
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... CNVSTR0 T A AV+ AGND VREF1 VRGND1 ADC1 AIN1 1Msps D AIN1G (16-Bit VBGAP1 CNVSTR1 Figure 1.3. C8051F064 / C8051F066 Block Diagram C8051F060/1/2/3/4/5/6/7 UART0 8 UART1 SFR Bus 0 SMBus SPI Bus 5 PCA 1 Timers 0, FLASH 1, 2,3,4 Memory 64k byte P0, P1, P2, (C8051F064) P3 Latches C 32k byte (C8051F066 256 byte ...
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... C8051F060/1/2/3/4/5/6/7 VDD VDD Digital Power VDD DGND DGND Analog Power DGND AV+ AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD Monitor WDT MONEN XTAL1 External Oscillator XTAL2 Circuit System Clock Trimmed Internal Oscillator VREF VREF AVDD AGND ...
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... With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5 shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks Silicon Labs (25 MHz clk) Figure 1.5. Comparison of Peak MCU Execution Speeds C8051F060/1/2/3/4/5/6/7 2 2 Microchip Philips ...
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... C8051F060/1/2/3/4/5/6/7 1.1.3. Additional Features The C8051F06x MCU family includes several key enhancements to the CIP-51 core and peripherals to improve overall performance and ease of use in end applications. The extended interrupt handler provides 22 interrupt sources into the CIP-51, allowing the numerous ana- log and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...
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... The CIP-51 in the C8051F060/1/2/3/4/5/6/7 MCUs additionally has an on-chip 4 kB RAM block. The on- chip 4 kB block can be addressed over the entire 64 k external data memory address range (overlapping 4 k boundaries) ...
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... JTAG port, and a target application board with a C8051F060 MCU installed. All of the necessary communication cables and a wall-mount power supply are also supplied with the development kit. Silicon Labs’ debug environment is a vastly supe- rior configuration for developing and debugging embedded applications compared to standard MCU emu- lators, which use on-board " ...
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... Programmable Digital I/O and Crossbar Three standard 8051 Ports (0, 1, and 2) are available on the MCUs. The C8051F060/2/4/6 have 4 addi- tional 8-bit ports ( and 7), and a 3-bit port (port 4) for a total of 59 general-purpose I/O Pins. The Ports behave like the standard 8051 with a few enhancements. ...
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... C8051F060/1/2/3/4/5/6/7 1.5. Programmable Counter Array The C8051F06x MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with 6 programmable capture/compare modules. The timebase is clocked from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow, an External Clock Input (ECI pin), the system clock, or the external oscillator source divided by 8 ...
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... Controller Area Network The C8051F060/1/2/3 devices feature a Controller Area Network (CAN) controller that implements serial communication using the CAN protocol. The CAN controller facilitates communication on a CAN network in accordance with the Bosch specification 2.0A (basic CAN) and 2.0B (full CAN). The CAN controller con- sists of a CAN Core, Message RAM (separate from the C8051 RAM), a message handler state machine, and control registers ...
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... C8051F060/1/2/3/4/5/6/7 1.7. Serial Ports The C8051F06x MCU Family includes two Enhanced Full-Duplex UARTs, an enhanced SPI Bus, and SMBus/I2C. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little intervention by the CPU. The serial buses do not "share" ...
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... Analog to Digital Converters The C8051F060/1/2/3/4/5/6/7 devices have two on-chip 16-bit SAR ADCs (ADC0 and ADC1), which can be used independently in single-ended mode, or together in differential mode. ADC0 and ADC1 can directly access on-chip or external RAM, using the DMA interface. With a maximum throughput of 1 Msps, the ADCs offer 16 bit performance with two available linearity grades ...
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... Analog to Digital Converter The C8051F060/1/2/3 devices have an on-board 10-bit SAR ADC (ADC2) with a 9-channel input multi- plexer and programmable gain amplifier. This ADC features a 200 ksps maximum throughput and true 10- bit performance with an INL of ±1LSB. Eight input pins are available for measurement and can be pro- grammed as single-ended or differential inputs ...
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... DAC output updates to be forced by a software write or scheduled on a Timer overflow. The DAC voltage reference is supplied from the dedicated VREFD input pin on C8051F060/2 devices or via the VREF2 pin on C8051F061/3 devices, which is shared with ADC2. The DACs are espe- cially useful as references for the comparators or offsets for the differential inputs of the ADCs ...
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... C8051F060/1/2/3/4/5/6/7 1.11. Analog Comparators The C8051F060/1/2/3/4/5/6/7 MCUs include three analog comparators on-chip. The comparators have software programmable hysteresis and response time. Each comparator can generate an interrupt on its rising edge, falling edge, or both. The interrupts are capable of waking up the MCU from sleep mode, and Comparator 0 can be used as a reset source ...
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... Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051F060/1/2/3/4/5/6/7 * Conditions Min ...
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... C8051F060/1/2/3/4/5/6/7 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics -40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Analog Supply Voltage (AV+, (Note 1) AVDD) Digital Supply Voltage (VDD) Analog-to-Digital Supply Delta (|VDD - AV+| or |VDD - AVDD|) Supply Current from Analog Internal REF, ADC, DAC, Com- Peripherals (active) parators all enabled ...
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... XTAL2 MONEN VREF VREF0 C8051F060/1/2/3/4/5/6/7 Table 4.1. Pin Definitions F065 Type Description F067 26, 40, Digital Supply Voltage. Must be tied to +2 +3.6 V. 27, 39, Digital Ground. Must be tied to Ground 10, Analog Supply Voltage. Must be tied Analog Supply Voltage. Must be tied to +2.7 to +3.6 V. ...
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... C8051F060/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F060 F061 F064 F062 F063 F066 VRGND0 VBGAP0 VREF1 VRGND1 VBGAP1 VREF2 2 62 VREFD 3 AIN0 AIN0G AIN1 AIN1G CNVSTR0 CNVSTR1 CANTX 94 59 CANRX 95 60 DAC0 25 17 DAC1 F065 Type Description ...
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... Port 1.4. See Port Input/Output section for complete A In description. ADC2 Input Channel 4 (C8051F060/1/2/3 Only I/O Port 1.5. See Port Input/Output section for complete A In description. ADC2 Input Channel 5 (C8051F060/1/2/3 Only I/O Port 1.6. See Port Input/Output section for complete A In description. ADC2 Input Channel 6 (C8051F060/1/2/3 Only I/O Port 1 ...
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... C8051F060/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F060 F061 F064 F062 F063 F066 P4.5/ALE 93 93 P4.6/ P4.7/ P5.0/ P5.1/ F065 Type Description F067 36 D I/O Port 2.5. See Port Input/Output section for complete description. ...
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... A7 P7.0/AD0m P7.1/AD1m C8051F060/1/2/3/4/5/6/7 F065 Type Description F067 D I/O Port 5.2. See Port Input/Output section for complete description. D I/O Port 5.3. See Port Input/Output section for complete description. D I/O Port 5.4. See Port Input/Output section for complete description. D I/O Port 5.5. See Port Input/Output section for complete description ...
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... C8051F060/1/2/3/4/5/6/7 Table 4.1. Pin Definitions (Continued) Pin Numbers Name F060 F061 F064 F062 F063 F066 P7.2/AD2m P7.3/AD3m P7.4/AD4m P7.5/AD5m P7.6/AD6m P7.7/AD7m 25, 94 F065 Type Description F067 D I/O Port 7.2. See Port Input/Output section for complete description. D I/O Port 7.3. See Port Input/Output section for complete description ...
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... AGND 10 AV+ 11 CNVSTR1 12 AVDD 13 AGND 14 CNVSTR0 15 AV+ 16 AGND 17 AIN0 18 AIN0G 19 VRGND0 20 VREF0 21 VBGAP0 22 AGND 23 AV+ 24 DAC0 25 Figure 4.1. C8051F060 / C8051F062 Pinout Diagram (TQFP-100) C8051F060/1/2/3/4/5/6/7 C8051F060/F062 Rev. 1.2 75 P6.5/A13m/A5 74 P6.6/A14m/A6 73 P6.7/A15m/A7 72 P7.0/AD0m/D0 71 P7.1/AD1m/D1 70 P7.2/AD2m/D2 69 P7.3/AD3m/D3 68 P7.4/AD4m/D4 67 P7.5/AD5m/D5 66 P7.6/AD6m/D6 65 P7.7/AD7m/D7 64 VDD 63 DGND 62 P0 ...
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... C8051F060/1/2/3/4/5/6 VREF 4 VBGAP1 5 VREF1 6 VRGND1 7 AIN1G 8 AIN1 9 AGND 10 AV+ 11 CNVSTR1 12 AVDD 13 AGND 14 CNVSTR0 15 AV+ 16 AGND 17 AIN0 18 AIN0G 19 VRGND0 20 VREF0 21 VBGAP0 22 AGND 23 AV Figure 4.2. C8051F064 / C8051F066 Pinout Diagram (TQFP-100) 46 C8051F064/F066 Rev. 1.2 75 P6.5/A13m/A5 74 P6.6/A14m/A6 73 P6.7/A15m/A7 72 P7.0/AD0m/D0 71 P7.1/AD1m/D1 70 P7.2/AD2m/D2 69 P7.3/AD3m/D3 68 P7.4/AD4m/D4 67 P7.5/AD5m/ ...
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... PIN 1 DESIGNATOR Figure 4.3. TQFP-100 Package Drawing C8051F060/1/2/3/4/5/6 Rev. 1.2 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0. 16. 14. 0. 16. 14. 0.45 0.60 0.75 47 ...
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... C8051F060/1/2/3/4/5/6/7 VBGAP1 1 VREF1 2 VRGND1 3 AIN1G 4 AIN1 5 AGND 6 AV+ 7 CNVSTR1 8 CNVSTR0 9 AV+ 10 AGND 11 AIN0 12 AIN0G 13 VRGND0 14 VREF0 15 VBGAP0 16 Figure 4.4. C8051F061 / C8051F063 Pinout Diagram (TQFP-64) 48 C8051F061/063 Rev. 1.2 48 P0.3 47 P0.4 46 P0.5 45 P0.6 44 P0.7 43 P2.0 42 P2.1 41 P2.2 40 VDD 39 DGND 38 P2.3 37 P2.4 36 P2 ...
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... VREF1 2 VRGND1 3 AIN1G 4 AIN1 5 AGND 6 AV+ 7 CNVSTR1 8 C8051F065/067 CNVSTR0 9 AV+ 10 AGND 11 AIN0 12 AIN0G 13 VRGND0 14 VREF0 15 VBGAP0 16 Figure 4.5. C8051F065 / C8051F067 Pinout Diagram (TQFP-64) C8051F060/1/2/3/4/5/6/7 Rev. 1.2 48 P0.3 47 P0.4 46 P0.5 45 P0.6 44 P0.7 43 P2.0 42 P2.1 41 P2.2 40 VDD 39 DGND 38 P2.3 37 P2.4 36 P2.5 35 P2 ...
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... C8051F060/1/2/3/4/5/6 PIN 1 DESIGNATOR Figure 4.6. TQFP-64 Package Drawing Rev. 1.2 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 - 1.05 b 0.17 0.22 0. 12. 10. 0. 12. 10. 0.45 0.60 0.75 ...
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... ADCs (ADC0 and ADC1) The ADC subsystem for the C8051F060/1/2/3/4/5/6/7 consists of two 1 Msps, 16-bit successive-approxi- mation-register ADCs with integrated track-and-hold, a Programmable Window Detector, and a DMA inter- face (see block diagrams in Figure 5.1 and Figure 5.2). The ADCs can be configured as two separate, single-ended ADCs differential pair ...
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... C8051F060/1/2/3/4/5/6/7 16-Bit AIN0 SAR ADC0 AIN0G 16-Bit AIN1 SAR ADC1 AIN1G ADC1H DMA Interface ADC0GTH Figure 5.2. 16-bit ADC0 and ADC1 Data Path Diagram 5.1. Single-Ended or Differential Operation ADC0 and ADC1 can be programmed to operate independently as single-ended ADCs, or together to accept a differential input. In single-ended mode, the ADCs can be configured to sample simultaneously use different conversion speeds ...
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... If an ADC is not being used, the BIASEn bit can be set to logic 0 to conserve power. The electrical specifications for the Voltage References are given in Table 5.3. External Voltage Reference VREFn 47F 0.1F VRGNDn VBGAPn 0.1F Recommended Bypass Capacitors Figure 5.3. Voltage Reference Block Diagram C8051F060/1/2/3/4/5/6/7 ADCn Ref Bias x2 Rev. 1.2 1.25V Band-Gap EN REFnCN 53 ...
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... C8051F060/1/2/3/4/5/6/7 5.3. ADC Modes of Operation ADC0 and ADC1 have a maximum conversion speed of 1 Msps. The conversion clocks for the ADCs are derived from the system clock. The ADCnSC bits in the ADCnCF register determine how many system clocks (from 1 to 16) are used for each conversion clock. ...
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... SYSCLK 0001 40*t SYSCLK 0010 58*t SYSCLK 0011 78*t SYSCLK 0100 97*t SYSCLK 0101 115*t SYSCLK 0110 134*t SYSCLK 0111 152*t SYSCLK C8051F060/1/2/3/4/5/6/7 t Conv Convert t Conv Track Convert t Conv Convert ) Conv ADnSC3-0 ADCnTM = 0 38*t 1000 171*t SYSCLK 72*t 1001 189*t SYSCLK ...
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... C8051F060/1/2/3/4/5/6/7 5.3.3. Settling Time Requirements The ADC requires a minimum tracking time before an accurate conversion can be performed. This tracking time is determined by the ADC input resistance, the ADC sampling capacitance, any external source resis- tance, and the accuracy required for the conversion. Figure 5.5 shows the equivalent ADC input circuits for both Differential and Single-ended modes ...
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... For single-ended mode, the ADC0 Data Word is stored in ADC0H and ADC0L, while the ADC1 Data Word is stored in ADC1H and ADC1L. In differential mode, the combined ADC Data Word is stored in ADC0H and ADC0L, and is a 2’s complement number. ADC1’s Data Word (single-ended) is also stored in ADC1H and ADC1L. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W ...
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... C8051F060/1/2/3/4/5/6/7 Figure 5.7. ADC0CF: ADC0 Configuration Register R/W R/W R/W AD0SC3 AD0SC2 AD0SC1 Bit7 Bit6 Bit5 Bits 7-4: AD0SC3-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is divided down from the system clock according to the AD0SC bits (AD0SC3-0). The number of system clocks used for each SAR conversion clock is equal to AD0SC + 1 ...
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... No Effect 1: Initiates a linearity calibration if ADC1 is idle Bit 0: AD1OCAL: Offset Calibration. Read: 0: Offset Calibration is completed or not yet started. 1: Offset Calibration is in progress. Write Effect. 1: Initiates an offset calibration if ADC1 is idle. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W AD1SC0 AD1SCAL AD1GCAL AD1LCAL Bit4 Bit3 Bit2 Rev. 1.2 ...
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... C8051F060/1/2/3/4/5/6/7 Figure 5.9. ADC0CN: ADC0 Control Register R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY Bit7 Bit6 Bit5 Bit 7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions or calibrations. Bit 6: AD0TM: ADC Track Mode Bit. ...
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... Tracking started by the overflow of Timer 2 and is followed by the conversion. xx1: Tracking starts with the write of ‘1’ to AD0BUSY and is followed by the conversion. See Figure 5.4 and Table 5.1 for conversion timing parameters. Bit 0: RESERVED: Write to 0b. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W ...
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... C8051F060/1/2/3/4/5/6/7 Figure 5.11. REF0CN: Reference Control Register 0 R/W R/W R Bit7 Bit6 Bit5 Bits7-2: RESERVED. Read = 000000b; Write = 000000b. Bit1: BIASE0: ADC0 Bias Generator Enable Bit. (Must be ‘1’ if using ADC0). 0: ADC0 Internal Bias Generator Off. 1: ADC0 Internal Bias Generator On. Bit0: REFBE0: Internal Reference Buffer for ADC0 Enable Bit. ...
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... Bit6 Bit5 Bits 7-0: ADC0 Data Word High-Order Bits. Figure 5.14. ADC0L: ADC0 Data Word LSB Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: ADC0 Data Word Low-Order Bits. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W ...
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... C8051F060/1/2/3/4/5/6/7 Figure 5.15. ADC0 Data Word Example 16-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows: Example: ADC0 Data Word Conversion Map, AIN0 Input in Single-Ended Mode (AMX0SL = 0x00) AIN0-AIN0G (Volts) VREF * (65535/65536) VREF / 2 VREF * (32767/65536) 0 Example: ADC0 Data Word Conversion Map, AIN0-AIN1 Differential Input Pair ...
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... Gain -------------- - Code = Vin VREF For differential mode, the differential data word appears in ADC0H and ADC0L. The single- ended ADC1 results are always present in ADC1H and ADC1L, regardless of the operating mode. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W ...
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... C8051F060/1/2/3/4/5/6/7 5.4. Calibration The ADCs are calibrated for linearity, offset, and gain in production. ADC0 and ADC1 can also be indepen- dently calibrated for each of these parameters in-system. Calibrations are initiated using bits in the ADC0 or ADC1 Configuration Register. The calibration coefficients can be accessed using the ADC Calibration Pointer Register (ADC0CPT, Figure 5 ...
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... Gain Register (13 Bits) 0x1FFF 0x1000 0x0000 Gain Register 0x1000 -------------------------------------------------------- - Slope Change Figure 5.21. Offset and Gain Calibration Block Diagram Offset - + AINn AINnG C8051F060/1/2/3/4/5/6/7 -3.125% * VREF 0 +3.125% * VREF – 3.125% VREF 8192 Approximate Slope Change +3.125% 0 -3.125% – ...
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... C8051F060/1/2/3/4/5/6/7 Figure 5.22. ADC0CPT: ADC Calibration Pointer Register R/W R/W R/W INCR ADCSEL CPTR5 Bit7 Bit6 Bit5 Bit 7: INCR: Pointer Address Automatic Increment. 0: Disable Auto-Increment. 1: Enable Auto-Increment. CPTR5-0 will automatically be incremented after each read or write to ADC0CCF. Bit 6: ADCSEL: ADC Calibration Coefficient Select. ...
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... Bits 7-0: High byte of ADC0 Greater-Than Data Word. Figure 5.25. ADC0GTL: ADC0 Greater-Than Data Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: Low byte of ADC0 Greater-Than Data Word. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W ...
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... C8051F060/1/2/3/4/5/6/7 Figure 5.26. ADC0LTH: ADC0 Less-Than Data High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: High byte of ADC0 Less-Than Data Word. Figure 5.27. ADC0LTL: ADC0 Less-Than Data Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: Low byte of ADC0 Less-Than Data Word. ...
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... Given: AMX0SL = 0x00, ADC0LTH:ADC0LTL = 0x2000, ADC0GTH:ADC0GTL = 0x1000. An ADC0 End of Conversion will cause an ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x2000 and > 0x1000. C8051F060/1/2/3/4/5/6/7 Input Voltage ADC0 Data (AIN0 - AIN0G) Word REF x (65535/65536) 0xFFFF 0x2001 REF x (8192/65536) ...
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... C8051F060/1/2/3/4/5/6/7 Figure 5.29. 16-Bit ADC0 Window Interrupt Example: Differential Data Input Voltage ADC0 Data (AIN0 - AIN1) Word REF x (32767/32768) 0x7FFF AD0WINT not affected 0x1001 REF x (4096/32768) 0x1000 ADC0LTH:ADC0LTL 0x0FFF AD0WINT=1 0x0000 REF x (-1/32768) 0xFFFF ADC0GTH:ADC0GTL 0xFFFE AD0WINT not affected 0x8000 -REF ...
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... Clocks Track/Hold Acquisition Time Throughput Rate Aperture Delay External CNVST Signal RMS Aperture Jitter External CNVST Signal Analog Inputs Input Voltage Range Single-Ended (AINn - AINnG) Differential (AIN0 - AIN1) Input Capacitance C8051F060/1/2/3/4/5/6/7 Min Typ 16 ±0.75 ±0.5 ±1.5 ±1 ±0.5 0.1 0.008 0.5 ...
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... C8051F060/1/2/3/4/5/6/7 Table 5.2. 16-Bit ADC0 and ADC1 Electrical Characteristics (Continued) VDD = 3.0 V, AV+ = 3.0 V, AVDD = 3.0 V, VREF = 2.50 V (REFBE=0), -40 to +85 °C unless otherwise specified Parameter Conditions Operating Input Range AIN0 or AIN1 AIN0G or AIN1G (DC Only) Power Specifications Power Supply Current (each Operating Mode, 1 Msps ...
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... Instruction Buffer at address DMA0IPT when the instruction word is written to DMA0IDT. Reading the register DMA0IDT will return the instruction word at location DMA0IPT. After a write or read operation on DMA0IDT, the DMA0IPT register is automatically incremented to the next Instruction Buffer location. C8051F060/1/2/3/4/5/6/7 Figure 6.1. DMA0 Block Diagram DMA0CF DMA0CN ...
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... XRAM by the DMA Control Logic occur when the processor core is not accessing the on-chip XRAM. This ensures that the DMA will not interfere with processor instruction timing. Off-chip XRAM access (only available on the C8051F060/2/4/6) is controlled by the DMA0HLT bit in DMA0CF (DMA Configuration Register, Figure 6.5). The DMA will have full access to off-chip XRAM when this bit is ‘ ...
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... Figure 6.2. Figure 6.2. DMA Mode 0 Operation INSTRUCTION BUFFER (64 Bytes) 0x3F ... 0x03 00000000 0x02 00110000 0x01 01000000 DMA0BND 0x00 00010000 C8051F060/1/2/3/4/5/6/7 XRAM ADC1L ADC1H DMA0CSH:L = 0x0000 ADC0L ADC0H (Diff.) DMA0CSH:L = DMA0CTH ADC0L ADC0H ADC1L ADC1H ADC0L ADC0H DMA0CSH:L = DMA0CTH:L ADC0L (Diff.) ADC0H (Diff ...
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... C8051F060/1/2/3/4/5/6/7 6.5. Instruction Execution in Mode 1 When the DMA interface begins an operation cycle, the DMA Instruction Status Register (DMA0ISW, Figure 6.9) is loaded with the address contained within the DMA Instruction Boundary Register (DMA0BND, Figure 6.8). The instruction is fetched from the Instruction Buffer, and the DMA Control Logic waits for data from the appropriate ADC(s) ...
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... DMA’s data buffer is not empty, an overflow warning flag is generated second conversion data word becomes available before the DMA’s data buffer is written to XRAM, the data in the ADC’s data regis- ters is over-written with the new data word, and a data overflow error flag is generated. C8051F060/1/2/3/4/5/6/7 Rev. 1.2 Section “6.3. XRAM ...
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... C8051F060/1/2/3/4/5/6/7 Figure 6.4. DMA0CN: DMA0 Control Register 3 SFR Page: 0xD8 (bit addressable) SFR Address: R/W R/W R/W DMA0EN DMA0INT DMA0MD DMA0DE1 DMA0DE0 DMA0DOE DMA0DO1 DMA0DO0 00000000 Bit7 Bit6 Bit5 Bit 7: DMA0EN: DMA0 Enable. Write: 0: Stop DMA0 Operations. 1: Begin DMA0 Operations. Read: 0: DMA0 is Idle ...
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... Bit7 Bit6 Bit5 Bit 7: DMA0HLT: Halt DMA0 Off-Chip XRAM Access (C8051F060/2/4/6 Only). 0: DMA0 has complete access to off-chip XRAM. 1: Processor core has complete access to off-chip XRAM. DMA0 will wait until this bit is ‘0’ before writing to off-chip XRAM locations. Bit 6: DMA0XBY: Off-chip XRAM Busy Flag (C8051F060/2/4/6 Only). ...
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... C8051F060/1/2/3/4/5/6/7 Figure 6.6. DMA0IPT: DMA0 Instruction Write Address Register 3 SFR Page: 0xDD SFR Address R Bit7 Bit6 Bit5 Bits 7-6: Unused. Bits 5-0: DMA0 instruction address to write (or read). When DMA0IDT is written or read, this register will be incremented to point to the next instruction address. Figure 6.7. DMA0IDT: DMA0 Instruction Write Data Register ...
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... Figure 6.9. DMA0ISW: DMA0 Instruction Status Register 3 SFR Page: 0xFE SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits 7-6: Unused. Bits 5-0: Contains the address of the current DMA0 Instruction to be executed. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 ...
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... C8051F060/1/2/3/4/5/6/7 Figure 6.10. DMA0DAH: DMA0 Data Address Beginning MSB Register 3 SFR Page: 0xDA SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: DMA0 Address Beginning High-Order Bits. Figure 6.11. DMA0DAL: DMA0 Data Address Beginning LSB Register 3 SFR Page: 0xD9 SFR Address: ...
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... Bits 7-0: DMA0 Repeat Counter High-Order Bits. Figure 6.17. DMA0CSL: DMA0 Repeat Counter LSB Register 3 SFR Page: 0xFB SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: DMA0 Repeat Counter Low-Order Bits. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
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... C8051F060/1/2/3/4/5/6/7 86 Rev. 1.2 ...
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... ADC (ADC2, C8051F060/1/2/3) The ADC2 subsystem for the C8051F060/1/2/3 consists of an analog multiplexer (referred to as AMUX2), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and pro- grammable window detector (see block diagram in Figure 7.1). The AMUX2, data conversion modes, and window detector can all be configured from within software via the Special Function Registers shown in Figure 7 ...
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... C8051F060/1/2/3/4/5/6/7 7.1. Analog Multiplexer The analog multiplexer (AMUX2) selects the inputs to the ADC, allowing any of the pins on Port measured in single-ended mode differential pair. Additionally, the on-chip temperature sensor may be selected as a single-ended input. The ADC2 input channels are configured and selected in the AMX2CF and AMX2SL registers as described in Figure 7 ...
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... AD2INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, low byte overflows are used if the timer is in 8-bit mode; and high byte overflows are used if the timer is in 16- bit mode. See Section “24. Timers” on page 287 C8051F060/1/2/3/4/5/6/7 Slope (V / deg C) Offset ...
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... C8051F060/1/2/3/4/5/6/7 7.2.2. Tracking Modes The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode. In its default state, the ADC2 input is continuously tracked, except when a conversion is in progress. When the AD2TM bit is logic 1, ADC2 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track- ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR2 signal is used to ini- tiate conversions in low-power tracking mode, ADC2 tracks only when CNVSTR2 is low ...
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... ADC resolution in bits (10). Figure 7.4. ADC2 Equivalent Input Circuits Differential Mode MUX Select P1 MUX Input MUX SAMPLE P1 MUX MUX Select C8051F060/1/2/3/4/5/6/7 . See Table 7.1 for ADC2 minimum settling time requirements. MUX n 2 ------ - = TOTAL SAMPLE SA Single-Ended Mode MUX Select P1 ...
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... C8051F060/1/2/3/4/5/6/7 Figure 7.5. AMX2CF: AMUX2 Configuration Register 2 SFR Page: 0xBA SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits 7-4: UNUSED. Read = 0000b; Write = don’t care. Bit 3: AIN67IC: AIN2.6, AIN2.7 Input Pair Configuration Bit. 0: AIN2.6 and AIN2.7 are independent, single-ended inputs. ...
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... AIN2.1 0010 AIN2.2 0011 AIN2.3 0100 AIN2.4 0101 AIN2.5 0110 AIN2.6 0111 AIN2.7 Temperature 1xxx Sensor C8051F060/1/2/3/4/5/6/7 R/W R/W R/W - AMX2AD3 AMX2AD2 AMX2AD1 AMX2AD0 00000000 Bit4 Bit3 Bit2 AMX2AD3-0 0000 +(AIN2.0) -(AIN2.1) AIN01IC = 0 0001 +(AIN2.1) -(AIN2.0) 0010 +(AIN2.2) -(AIN2.3) AIN23IC = 0 0011 +(AIN2 ...
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... C8051F060/1/2/3/4/5/6/7 Figure 7.7. ADC2CF: ADC2 Configuration Register 2 SFR Page: 0xBC SFR Address: R/W R/W R/W AD2SC4 AD2SC3 AD2SC2 Bit7 Bit6 Bit5 Bits7-3: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where ADSC refers to the 5-bit value held in bits AD2SC4-AD2SC0 ...
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... ADC2 Data Word Low-Order Bits. For AD2LJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit Data Word. For AD2LJST = 1: Bits 7-6 are the lower 2 bits of the 10-bit Data Word. Bits 5-0 will always read ‘0’. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W ...
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... C8051F060/1/2/3/4/5/6/7 Figure 7.10. ADC2CN: ADC2 Control Register 2 SFR Page: 0xE8 (bit addressable) SFR Address: R/W R/W R/W AD2EN AD2TM AD2INT Bit7 Bit6 Bit5 Bit 7: AD2EN: ADC2 Enable Bit. 0: ADC2 Disabled. ADC2 is in low-power shutdown. 1: ADC2 Enabled. ADC2 is active and ready for data conversions. ...
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... Bits7-0: High byte of ADC2 Greater-Than Data Word. Figure 7.12. ADC2GTL: ADC2 Greater-Than Data Low Byte Register 2 SFR Page: 0xC4 SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low byte of ADC2 Greater-Than Data Word. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
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... C8051F060/1/2/3/4/5/6/7 Figure 7.13. ADC2LTH: ADC2 Less-Than Data High Byte Register 2 SFR Page: 0xC7 SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: High byte of ADC2 Less-Than Data Word. Figure 7.14. ADC2LTL: ADC2 Less-Than Data Low Byte Register 2 SFR Page: 0xC6 SFR Address: ...
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... AD2WINT not affected 0x2040 VREF x (128/1024) 0x2000 ADC2LTH:ADC2LTL 0x1FC0 0x1040 VREF x (64/1024) 0x1000 ADC2GTH:ADC2GTL 0x0FC0 AD2WINT not affected 0x0000 0 C8051F060/1/2/3/4/5/6/7 ADC2H:ADC2L Input Voltage (P1.x - AGND) VREF x (1023/1024) 0x03FF 0x0081 VREF x (128/1024) 0x0080 0x007F AD2WINT=1 0x0041 VREF x (64/1024) 0x0040 0x003F 0x0000 0 ...
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... C8051F060/1/2/3/4/5/6/7 7.3.2. Window Detector In Differential Mode Figure 7.17 shows two example window comparisons for right-justified, differential data, with ADC2LTH:ADC2LTL = 0x0040 (+64d) and ADC2GTH:ADC2GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are rep- resented as 10-bit 2’ ...
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... Offset Error (Note 1) Temp = 0 °C Slope Slope Error (Note 1) Power Specifications Power Supply Current (VDD sup- Operating Mode, 200 ksps plied to ADC2) Power Supply Rejection Note 1: Represents one standard deviation from the mean value. C8051F060/1/2/3/4/5/6/7 Min Typ 10 ±0.5 ±0.5 -12 1 - ...
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... C8051F060/1/2/3/4/5/6/7 102 Rev. 1.2 ...
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... DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) The C8051F060/1/2/3 devices include two on-chip 12-bit voltage-mode Digital-to-Analog Converters (DACs). Each DAC has an output swing (VREF-1LSB) for a corresponding input code range of 0x000 to 0xFFF. The DACs may be enabled/disabled via their corresponding control registers, DAC0CN and DAC1CN. While disabled, the DAC output is maintained in a high-impedance state, and the DAC sup- ply current falls to 1 µ ...
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... C8051F060/1/2/3/4/5/6/7 8.1. DAC Output Scheduling Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. The following examples are written in terms of DAC0, but DAC1 operation is identical. 8.1.1. Update Output On-Demand In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” write to the high- byte of the DAC0 data register (DAC0H) ...
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... Bit5 Bits7-0: DAC0 Data Word Most Significant Byte. Figure 8.3. DAC0L: DAC0 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Least Significant Byte. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
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... C8051F060/1/2/3/4/5/6/7 Figure 8.4. DAC0CN: DAC0 Control Register R/W R/W R/W DAC0EN - - Bit7 Bit6 Bit5 Bit7: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. 1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational. Bits6-5: UNUSED. Read = 00b; Write = don’t care. ...
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... Bit5 Bits7-0: DAC1 Data Word Most Significant Byte. Figure 8.6. DAC1L: DAC1 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Least Significant Byte. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
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... C8051F060/1/2/3/4/5/6/7 Figure 8.7. DAC1CN: DAC1 Control Register R/W R/W R/W DAC1EN - - Bit7 Bit6 Bit5 Bit7: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. 1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational. Bits6-5: UNUSED. Read = 00b; Write = don’t care. ...
Page 109
... Output Voltage Swing Startup Time Analog Outputs Load Regulation I L 0xFFF Power Consumption (each DAC) Power Supply Current (AV+ Data Word = 0x7FF supplied to DAC) C8051F060/1/2/3/4/5/6/7 = 0.01mA to 0.3mA at code Rev. 1.2 Min Typ Max Units 12 bits ±1.5 LSB ±1 LSB 250 µ ...
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... C8051F060/1/2/3/4/5/6/7 110 Rev. 1.2 ...
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... Voltage Reference 2 (C8051F060/2) The voltage reference circuitry offers full flexibility in operating the ADC2 and DAC modules. Two voltage reference input pins allow ADC2 and the two DACs to reference an external voltage reference or the on- chip voltage reference output. ADC2 may also reference the analog power supply voltage, via the VREF multiplexer shown in Figure 9 ...
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... C8051F060/1/2/3/4/5/6/7 The temperature sensor connects to the highest order input of the ADC2 input multiplexer (see “7. 10-Bit ADC (ADC2, C8051F060/1/2/3)” on page ables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state, and any A/D measurements performed on the sensor while disabled result in meaningless data. ...
Page 113
... AV+ for the ADC2 voltage reference source. The electrical specifications for the Voltage Reference are given in Table 10.1. Figure 10.1. Voltage Reference Functional Block Diagram VDD External R Voltage Reference Circuit + 4.7F 0.1F Recommended Bypass Capacitors C8051F060/1/2/3/4/5/6/7 REF2CN AV VREF2 DAC0 Ref DAC1 VREF x2 REFBE Rev. 1.2 ADC2 ...
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... C8051F060/1/2/3/4/5/6/7 The temperature sensor connects to the highest order input of the ADC2 input multiplexer (see “7. 10-Bit ADC (ADC2, C8051F060/1/2/3)” on page ables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state, and any A/D measurements performed on the sensor while disabled result in meaningless data. ...
Page 115
... BIASE and REFBE must both be set to logic 1. If the internal reference is not used, REFBE may be set to logic 0. The electrical specifications for the Voltage Reference are given in Table 11.1. Figure 11.1. Voltage Reference Functional Block Diagram External Circuitry C8051F060/1/2/3/4/5/6/7 VREF x2 + 4.7F 0.1 ...
Page 116
... C8051F060/1/2/3/4/5/6/7 Figure 11.2. REF2CN: Reference Control Register 2 R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bits2-3: RESERVED. Must Write to 00b. Bit1: BIASE: ADC/DAC Bias Generator Enable Bit. (Must be ‘1’ if using ADC2 or DACs). 0: Internal Bias Generator Off. ...
Page 117
... CPnHYN1 CPnHYN0 Comparator Pin Assignments CP0 + P2.6 CP0 - P2.7 CP1 + P2.2 CP1 - P2.3 CPn + CP2 + P2.4 CP2 - P2.5 CPn - C8051F060/1/2/3/4/5/6/7 Section “18.1.5. Configuring Port 1 and 2 pins as Analog 165). Section “18.1.1. Crossbar Pin Assignment and VDD + SET SET CLR CLR (SYNCHRONIZER) GND ...
Page 118
... C8051F060/1/2/3/4/5/6/7 Comparator inputs can be externally driven from -0. (VDD) + 0.25 V without damage or upset. The complete electrical specifications for the Comparator are given in Table 12.1. The Comparator response time may be configured in software using the CPnMD1-0 bits in register CPT- nMD (see Figure 12.4). Selecting a longer response time reduces the amount of power consumed by the comparator ...
Page 119
... Inputs” on page 207). The inputs for Comparator are on Port 2 as follows: Comparator Input CP0 + CP0 - CP1 + CP1 - CP2 + CP2 - C8051F060/1/2/3/4/5/6/7 Section “13.3. Interrupt Handler” on page Section “18.1.3. Configuring Port Pins as Digital Port PIN P2.6 P2.7 P2.2 P2.3 P2.4 P2.5 Rev ...
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... C8051F060/1/2/3/4/5/6/7 Figure 12.3. CPTnCN: Comparator 0, 1, and 2 Control Register R/W R/W R/W CPnEN CPnOUT CPnRIF Bit7 Bit6 Bit5 SFR Address: CPT0CN: 0x88; CPT1CN: 0x88; CPT2CN: 0x88 SFR Pages: CPT0CN: page 1; CPT1CN: page 2; CPT2CN: page 3 Bit7: CPnEN: Comparator Enable Bit. (Please see note below.) 0: Comparator Disabled ...
Page 121
... Comparator falling-edge interrupt disabled. 1: Comparator falling-edge interrupt enabled. Bits3-2: UNUSED. Read = 00b, Write = don’t care. Bits1-0: CPnMD1-CPnMD0: Comparator Mode Select These bits select the response time for the Comparator. Mode CPnMD1 CPnMD0 C8051F060/1/2/3/4/5/6/7 R CPnFIE - - CPnMD1 Bit4 Bit3 Bit2 Notes 0 Fastest Response Time ...
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... C8051F060/1/2/3/4/5/6/7 Table 12.1. Comparator Electrical Characteristics VDD = 3.0 V, -40 to +85 °C unless otherwise specified. Parameter Conditions Response Time, CPn+ - CPn- = 100 mV Mode 0 CPn+ - CPn Response Time, CPn+ - CPn- = 100 mV Mode 1 CPn+ - CPn Response Time, CPn+ - CPn- = 100 mV Mode 2 CPn+ - CPn Response Time, ...
Page 123
... Fully Compatible with MCS-51 Instruction Set - 25 MIPS Peak Throughput with 25 MHz Clock - MHz Clock Frequency - 256 Bytes of Internal RAM - 59/24 General-Purpose I/O Pins C8051F060/1/2/3/4/5/6/7 Section 24), two full-duplex UARTs (see description in Section Section 26), and interfaces directly with the MCU’s - Extended Interrupt Handler - ...
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... C8051F060/1/2/3/4/5/6/7 The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 13.1 for a block diagram). The CIP-51 includes the following features: Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture ...
Page 125
... Section “16. Flash Memory” on page off-chip XRAM (or memory-mapped peripherals) via the MOVX instruction. Refer to Data Memory Interface and On-Chip XRAM” on page 187 C8051F060/1/2/3/4/5/6/7 177). The External Memory Interface provides a fast access to for details. Rev. 1.2 Section “17. External ...
Page 126
... C8051F060/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary Mnemonic Description ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to A ADDC A, Rn Add register to A with carry ADDC A, direct Add direct byte to A with carry ...
Page 127
... Exchange low nibble of indirect RAM with A CLR C Clear Carry CLR bit Clear direct bit SETB C Set Carry SETB bit Set direct bit CPL C Complement Carry CPL bit Complement direct bit ANL C, bit AND direct bit to Carry C8051F060/1/2/3/4/5/6/7 Data Transfer Boolean Manipulation Rev. 1.2 Clock Bytes Cycles ...
Page 128
... C8051F060/1/2/3/4/5/6/7 Table 13.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR complement of direct bit to Carry MOV C, bit Move direct bit to Carry MOV bit, C Move Carry to direct bit JC rel ...
Page 129
... LCALL and LJMP. The destination may be anywhere within the 64K-byte program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. C8051F060/1/2/3/4/5/6/7 Rev. 1.2 129 ...
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... Program Memory The CIP-51 has byte program memory space. The C8051F060/1/2/3/4/5 devices implement 64 k bytes of this program memory space as in-system re-programmable Flash memory, organized in a contig- uous block from addresses 0x0000 to 0xFFFF. Note: 1024 bytes (0xFC00 to 0xFFFF) of this memory are reserved, and are not available for user program storage ...
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... The stack depth can extend up to 256 bytes. The MCUs also have built-in hardware for a stack record which is accessed by the debug logic. The stack record is a 32-bit shift register, where each PUSH or increment SP pushes one record bit onto the register, C8051F060/1/2/3/4/5/6/7 Rev. 1.2 131 ...
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... C8051F060/1/2/3/4/5/6/7 and each CALL pushes two record bits onto the register. (A POP or decrement SP pops one record bit, and a RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can notify the debug software even with the MCU running at speed. ...
Page 133
... PAGES)” designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “(ALL PAGES)” designation, indicating these SFRs are accessible from all SFR pages regardless of the SFRPAGE register value. C8051F060/1/2/3/4/5/6/7 Figure 13.3. SFR Page Stack SFRPGCN Bit ...
Page 134
... C8051F060/1/2/3/4/5/6/7 13.2.6.3.SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51 is executing in-line code that is writing values to Port 5 (SFR “P5”, located at address 0xD8 on SFR Page 0x0F) ...
Page 135
... SFR Page by writing a new value to the SFRPAGE register at any time during the ADC2 ISR to access SFRs that are not on SFR Page 0x02. See Figure 13.5 below. Figure 13.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs SFRPAGE pushed to SFRNEXT C8051F060/1/2/3/4/5/6/7 SFR Page 0x02 Automatically pushed on stack in SFRPAGE on ADC2 interrupt ...
Page 136
... C8051F060/1/2/3/4/5/6/7 While in the ADC2 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the ADC2 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to access the PCA’ ...
Page 137
... SFR Page value 0x0F being used to access Port 5 before the ADC2 interrupt occurred. See Figure 13.7 below. Figure 13.7. SFR Page Stack Upon Return From PCA Interrupt SFRNEXT popped to SFRPAGE SFRLAST popped to SFRNEXT C8051F060/1/2/3/4/5/6/7 SFR Page 0x00 Automatically popped off of the stack on return from interrupt 0x02 SFRPAGE (ADC2) ...
Page 138
... C8051F060/1/2/3/4/5/6/7 On the execution of the RETI instruction in the ADC2 Window Comparator ISR, the value in SFRPAGE register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the Port 5 SFR bits as it did prior to the interrupts occurring. See Figure 13.8 below. Figure 13.8. SFR Page Stack Upon Return From ADC2 Window Interrupt ...
Page 139
... SFR page upon return from interrupt (unless SFR Stack was altered before a returning from the interrupt). SFRPAGE is the top byte of the SFR Page Stack, and push/pop events of this stack are caused by interrupts (and not by reading/writing to the SFRPAGE register) C8051F060/1/2/3/4/5/6/7 R/W R/W R/W ...
Page 140
... C8051F060/1/2/3/4/5/6/7 Figure 13.11. SFRNEXT: SFR Next Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFR- LAST is the third entry. The SFR stack bytes may be used to alter the context in the SFR Page Stack, and will not cause the stack to ‘ ...
Page 141
... RCAP4L SMB0CN SMB0STA SMB0DAT 0 1 CAN0STA SADEN0 AMX2CF (ALL PAGES ADC0CPT 0(8) 1(9) C8051F060/1/2/3/4/5/6/7 2(A) 3(B) 4(C) PCA0CPL0 PCA0CPH0 PCA0CPL1 DMA0CSL DMA0CSH DMA0BND XBR1 XBR2 XBR3 PCA0CPM1 PCA0CPM2 PCA0CPM3 CAN0TST DMA0DSL DMA0DSH DAC0H DAC0CN DAC1H DAC1CN RCAP2H TMR2L RCAP3H TMR3L RCAP4H ...
Page 142
... C8051F060/1/2/3/4/5/6/7 Table 13.2. Special Function Register (SFR) Memory Map (ALL PAGES SADDR0 (ALL PAGES EMI0TC EMI0CN (ALL PAGES SCON0 SBUF0 SPI0CFG 0 1 SCON1 SBUF1 SSTA0 (ALL PAGES TCON TMOD 1 CPT0CN CPT0MD 88 2 CPT1CN CPT1MD 3 CPT2CN CPT2MD F OSCICN (ALL PAGES) (ALL PAGES) ...
Page 143
... CAN0TST 0xDB CKCON 0x8E CLKSEL 0x97 CPT0CN 0x88 CPT0MD 0x89 CPT1CN 0x88 CPT1MD 0x89 CPT2CN 0x88 C8051F060/1/2/3/4/5/6/7 F ADC0 Calibration Coefficient 0 ADC0 Configuration 0 ADC0 Control F ADC0 Calibration Pointer 0 ADC0 Greater-Than High 0 ADC0 Greater-Than Low 0 ADC0 Data Word High 0 ADC0 Data Word Low ...
Page 144
... C8051F060/1/2/3/4/5/6/7 Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description CPT2MD 0x89 DAC0CN 0xD4 DAC0H 0xD3 DAC0L 0xD2 DAC1CN 0xD4 DAC1H 0xD3 DAC1L 0xD2 DMA0BND 0xFD DMA0CF 0xF8 ...
Page 145
... All Pages Program Status Word RCAP2H 0xCB RCAP2L 0xCA RCAP3H 0xCB RCAP3L 0xCA RCAP4H 0xCB RCAP4L 0xCA C8051F060/1/2/3/4/5/6/7 F Port 2 Input Mode F Port 2 Output Mode Configuration F Port 3 Output Mode Configuration F Port 4 Latch F Port 4 Output Mode Configuration F Port 5 Latch F Port 5 Output Mode Configuration ...
Page 146
... C8051F060/1/2/3/4/5/6/7 Table 13.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address SFR Page Description REF0CN 0xD1 REF1CN 0xD1 REF2CN 0xD1 RSTSRC 0xEF SADDR0 0xA9 SADEN0 0xB9 SBUF0 0x99 SBUF1 0x99 SCON0 0x98 ...
Page 147
... XBR3 0xE4 *1 Refers to a register in the C8051F060/2/4/6 only. *2 Refers to a register in the C8051F060/2 only. *3 Refers to a register in the C8051F061/3 only. *4 Refers to a register in the C8051F060/1/2/3 only. *5 Refers to a register in the C8051F064/5/6/7 only. C8051F060/1/2/3/4/5/6/7 2 Timer/Counter 4 Low F Port I/O Crossbar Control 0 F Port I/O Crossbar Control 1 ...
Page 148
... C8051F060/1/2/3/4/5/6/7 13.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys- tem function ...
Page 149
... Bit1: F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. Bit0: PARITY: Parity Flag. This bit is set the sum of the eight bits in the accumulator is odd and cleared if the sum is even. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W RS1 RS0 ...
Page 150
... C8051F060/1/2/3/4/5/6/7 Figure 13.17. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a second accumulator for certain arithmetic operations. ...
Page 151
... The exter- nal interrupt source must hold the input active until the interrupt request is recognized. It must then deacti- vate the interrupt request before execution of the ISR completes or another interrupt request will be generated. C8051F060/1/2/3/4/5/6/7 Rev. 1.2 151 ...
Page 152
... C8051F060/1/2/3/4/5/6/7 Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 0x002B Serial Peripheral Interface 0x0033 SMBus Interface 0x003B ADC0 Window 0x0043 Comparator Programmable Counter 0x004B Array Comparator 0 ...
Page 153
... DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. C8051F060/1/2/3/4/5/6/7 Rev. 1.2 153 ...
Page 154
... C8051F060/1/2/3/4/5/6/7 13.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). ...
Page 155
... Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. Bit0: PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W PS0 PT1 ...
Page 156
... C8051F060/1/2/3/4/5/6/7 Figure 13.21. EIE1: Extended Interrupt Enable 1 R/W R/W R/W EADC0 CP2IE CP1IE Bit7 Bit6 Bit5 Bit7: EADC0: Enable ADC0 End of Conversion Interrupt. This bit sets the masking of the ADC0 End of Conversion Interrupt. 0: Disable ADC0 Conversion Interrupt. 1: Enable interrupt requests generated by the ADC1 Conversion Interrupt. ...
Page 157
... Disable ADC1 Conversion Interrupt. 1: Enable interrupt requests generated by the ADC1 Conversion Interrupt. Bit0: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable all Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3 flag. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W EADC2 EWADC2 ET4 ...
Page 158
... C8051F060/1/2/3/4/5/6/7 Figure 13.23. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PADC0 PCP2 PCP1 Bit7 Bit6 Bit5 Bit7: PADC0: ADC End of Conversion Interrupt Priority Control. This bit sets the priority of the ADC0 End of Conversion Interrupt. 0: ADC0 End of Conversion interrupt set to low priority level. ...
Page 159
... ADC1 End of Conversion interrupt set to high priority level. Bit0: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupts. 0: Timer 3 interrupt set to low priority level. 1: Timer 3 interrupt set to high priority level. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W PADC2 PWADC2 PT4 ...
Page 160
... C8051F060/1/2/3/4/5/6/7 13.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped ...
Page 161
... Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’. 1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and all peripherals remain active.) See Note in Section “13.4.1. Idle C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W ...
Page 162
... C8051F060/1/2/3/4/5/6/7 162 Rev. 1.2 ...
Page 163
... I/O) (CNVSTR reset enable) Comparator0 CP0 CP0- Internal Clock Generator XTAL1 OSC XTAL2 C8051F060/1/2/3/4/5/6/7 “15. Oscillators” on page Reset” on page 165). Once the system clock source Figure 14.1. Reset Sources VDD Supply Monitor Supply + Reset - Timeout VDD Monitor reset enable ...
Page 164
... C8051F060/1/2/3/4/5/6/7 14.1. Power-on Reset The C8051F060/1/2/3/4/5/6/7 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the V RST to Table 14.1 for the Electrical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end of the 100 ms VDD Monitor timeout in order to allow the VDD supply to stabilize. The VDD Monitor reset is enabled and disabled using the external VDD monitor enable pin (MONEN) ...
Page 165
... If this period exceeds the programmed limit, a WDT reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN) shown in Figure 14.3. C8051F060/1/2/3/4/5/6/7 “15. Oscillators” on page 171) enables the Missing Clock Detector. “12. ...
Page 166
... C8051F060/1/2/3/4/5/6/7 14.7.1. Enable/Reset WDT The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica- tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. The WDT is enabled and reset as a result of any system reset. ...
Page 167
... Reading the WDTCN.[4] bit indicates the Watchdog Timer Status. 0: WDT is inactive. 1: WDT is active. Bits2-0: Watchdog Timeout Interval Bits. The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must be set to 0. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W R/W Bit4 Bit3 ...
Page 168
... C8051F060/1/2/3/4/5/6/7 Figure 14.4. RSTSRC: Reset Source Register R R/W R/W - CNVRSEF C0RSEF Bit7 Bit6 Bit5 Bit7: Reserved. Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag Write: 0: CNVSTR2 is not a reset source. 1: CNVSTR2 is a reset source (active low). Read: 0: Source of prior reset was not CNVSTR2. ...
Page 169
... RST Minimum /RST Low Time to Generate a System Reset /RST rising edge after VDD Reset Time Delay crosses V Missing Clock Detector Time- Time from last system clock to out reset initiation C8051F060/1/2/3/4/5/6/7 Conditions Min = 8.5 mA, VDD = 2 3.6 V 0.7 x VDD 1.0 1.0 2.40 threshold ...
Page 170
... C8051F060/1/2/3/4/5/6/7 170 Rev. 1.2 ...
Page 171
... VDD XTAL1 15.1. Programmable Internal Oscillator All C8051F060/1/2/3/4/5/6/7 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by Figure 15.2. OSCICL is factory calibrated to obtain a 24.5 MHz base frequency (f Electrical specifications for the precision internal oscillator are given in Table 15 ...
Page 172
... C8051F060/1/2/3/4/5/6/7 . Figure 15.2. OSCICL: Internal Oscillator Calibration Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: OSCICL: Internal Oscillator Calibration Register This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. The reset value is factory calibrated to generate an inter- nal oscillator frequency of 24 ...
Page 173
... Bit7 Bit6 Bit5 Bits7-1: Reserved. Bit0: CLKSL: System Clock Source Select Bit. 0: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits in OSCICN. 1: SYSCLK derived from the External Oscillator circuit. C8051F060/1/2/3/4/5/6/7 Conditions Min 24 R/W R/W R/W R Bit4 Bit3 ...
Page 174
... C8051F060/1/2/3/4/5/6/7 Figure 15.5. OSCXCN: External Oscillator Control Register R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Valid only when XOSCMD = 11x.). 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6-4: XOSCMD2-0: External Oscillator Mode Bits. ...
Page 175
... Assume VDD = 3.0 V and pF VDD ) = 150 If a frequency of roughly 50 kHz is desired, select the K Factor from the table in Figure 15 7. 7.7 / 150 = 0.051 MHz kHz Therefore, the XFCN value to use in this example is 010. C8051F060/1/2/3/4/5/6/7 Rev. 1.2 175 ...
Page 176
... C8051F060/1/2/3/4/5/6/7 176 Rev. 1.2 ...
Page 177
... Flash Memory The C8051F060/1/2/3/4/5/6/7 devices include on-chip, reprogrammable Flash memory for program code and non-volatile data storage. The C8051F060/1/2/3/4/5 include 128 bytes of Flash, and the C8051F066/7 include 128 bytes of Flash. The Flash memory can be programmed in-system, a sin- gle byte at a time, through the JTAG interface or by software using the MOVX write instructions. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1 ...
Page 178
... Step 9. Re-enable interrupts. Write/Erase timing is automatically controlled by hardware. Note that code execution in the 8051 is stalled while the Flash is being programmed or erased. Table 16.1. Flash Electrical Characteristics Parameter Flash Size * C8051F060/1/2/3/4/5 Flash Size * C8051F066/7 Endurance Erase Cycle Time Write Cycle Time * Includes 128-byte Scratch Pad Area † ...
Page 179
... The Scratchpad area is read or write/erase locked when all bits in the corresponding security byte are cleared to logic 0. On the C8051F060/1/2/3/4/5, the security lock bytes are located at 0xFBFE (Write/Erase Lock) and 0xFBFF (Read Lock), as shown in Figure 16.1. On the C8051F066/7, the security lock bytes are located at 0x7FFE (Write/Erase Lock) and 0x7FFF (Read Lock), as shown in Figure 16 ...
Page 180
... C8051F060/1/2/3/4/5/6/7 Figure 16.1. C8051F060/1/2/3/4/5 Flash Program Memory Map and Security Bytes Read and Write/Erase Security Bits (Bit 7 is MSB) Bit Memory Block 7 0xE000 - 0xFBFD 6 0xC000 - 0xDFFF 5 0xA000 - 0xBFFF 4 0x8000 - 0x9FFF 3 0x6000 - 0x7FFF 2 0x4000 - 0x5FFF 1 0x2000 - 0x3FFF 0 0x0000 - 0x1FFF Flash Read Lock Byte Bits7-0: Each bit locks a corresponding block of memory ...
Page 181
... The Flash Access Limit security feature (see Figure 16.3) protects proprietary program code and data from being read by software running on the C8051F060/1/2/3/4/5/6/7. This feature provides support for OEMs that wish to program the MCU with proprietary value-added firmware before distribution. The value-added firmware can be protected while allowing additional code to be programmed in remaining program memory space later ...
Page 182
... C8051F060/1/2/3/4/5/6/7 ing at 0x0000 up to (but excluding) the FAL address. Software in the upper partition can execute code in the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruc- tion. (Executing a MOVC instruction from the upper partition with a source address in the lower partition will always return a data value of 0x00 ...
Page 183
... Summary of Flash Security Options There are three Flash access methods supported on the C8051F060/1/2/3/4/5/6/7; 1) Accessing Flash through the JTAG debug interface, 2) Accessing Flash from firmware residing below the Flash Access Limit, and 3) Accessing Flash from firmware residing at or above the Flash Access Limit. ...
Page 184
... C8051F060/1/2/3/4/5/6/7 Figure 16.4. FLSCL: Flash Memory Control R/W R/W R/W FOSE FRAE Reserved Bit7 Bit6 Bit5 Bit 7: FOSE: Flash One-Shot Timer Enable This is the timer that turns off the sense amps after a Flash read. 0: Flash One-Shot Timer disabled. 1: Flash One-Shot Timer enabled (recommended setting.) ...
Page 185
... Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction. The location must be erased prior to writing data. 0: Write to Flash program memory disabled. MOVX write operations target External RAM. 1: Write to Flash program memory enabled. MOVX write operations target Flash memory. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W ...
Page 186
... C8051F060/1/2/3/4/5/6/7 186 Rev. 1.2 ...
Page 187
... External Data Memory Interface and On-Chip XRAM The C8051F060/1/2/3/4/5/6/7 MCUs include 4 k bytes of on-chip RAM mapped into the external data memory space (XRAM). In addition, the C8051F060/2/4/6 include an External Data Memory Interface which can be used to access off-chip memories and memory-mapped devices connected to the GPIO ports ...
Page 188
... C8051F060/1/2/3/4/5/6/7 17.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of four steps: 1. Enable the EMIF on the High Ports (P7, P6, P5, and P4). 2. Configure the Output Modes of the port pins as either push-pull or open-drain (push-pull is most common). 3. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic ‘ ...
Page 189
... ALE high and ALE low pulse width = 1 SYSCLK cycle. 01: ALE high and ALE low pulse width = 2 SYSCLK cycles. 10: ALE high and ALE low pulse width = 3 SYSCLK cycles. 11: ALE high and ALE low pulse width = 4 SYSCLK cycles. C8051F060/1/2/3/4/5/6/7 R/W R/W R/W PGSEL4 ...
Page 190
... C8051F060/1/2/3/4/5/6/7 17.4. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 17.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0] ...
Page 191
... Configuration is shown in Figure 17.4. See page 196 for more information about Non-multiplexed operation. Figure 17.4. Non-multiplexed Configuration Example A[15:0] (P5 and P6 D[7:0] (P7) F /RD (P4.6) /WR (P4.7) C8051F060/1/2/3/4/5/6/7 Section “17.6.1. Non-multiplexed Mode” on ADDRESS BUS V DD (Optional) 8 DATA BUS Rev. 1.2 A[15:0] 64K X 8 SRAM I/O[7:0] OE ...
Page 192
... C8051F060/1/2/3/4/5/6/7 17.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 17.5, based on the EMIF Mode bits in the EMI0CF register (Figure 17.2). These modes are summarized below. More infor- mation about the different modes can be found in 17.5.1. Internal XRAM Only When EMI0CF.[3:2] are set to ‘ ...
Page 193
... Port state directly. The lower 8-bits of the effective address A[7:0] are determined by the contents R1. • 16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. C8051F060/1/2/3/4/5/6/7 Rev. 1.2 193 ...
Page 194
... C8051F060/1/2/3/4/5/6/7 17.6. Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements. The Address Setup time, Address Hold time and /WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through EMI0TC, shown in Figure 17 ...
Page 195
... Table 17.1 lists the AC parameters for the External Memory Interface, and Figure 17.7 through Figure 17.12 show the timing diagrams for the different External Memory Interface modes and MOVX operations. C8051F060/1/2/3/4/5/6/7 Rev. 1.2 195 ...
Page 196
... C8051F060/1/2/3/4/5/6/7 17.6.1. Non-multiplexed Mode 17.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. Figure 17.7. Non-multiplexed 16-bit MOVX Timing ADDR[15:8] P5 ADDR[7:0] P6 DATA[7:0] P7 /WR P4.7 /RD P4.6 ADDR[15:8] P5 ADDR[7:0] P6 DATA[7:0] P7 /RD P4.6 /WR P4.7 196 Nonmuxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL ...
Page 197
... DATA[7:0] P7 /WR P4.7 /RD P4.6 ADDR[15:8] ADDR[7:0] P6 DATA[7:0] P7 /RD P4.6 /WR P4.7 C8051F060/1/2/3/4/5/6/7 Nonmuxed 8-bit WRITE without Bank Select P5 EMIF ADDRESS (8 LSBs) from EMIF WRITE DATA T WDS T T ACS ACW Nonmuxed 8-bit READ without Bank Select P5 EMIF ADDRESS (8 LSBs) from EMIF READ DATA ...
Page 198
... C8051F060/1/2/3/4/5/6/7 17.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. Figure 17.9. Non-multiplexed 8-bit MOVX with Bank Select Timing ADDR[15:8] P5 ADDR[7:0] P6 DATA[7:0] P7 /WR P4.7 /RD P4.6 ADDR[15:8] P5 ADDR[7:0] P6 DATA[7:0] P7 /RD P4.6 /WR P4.7 198 Nonmuxed 8-bit WRITE with Bank Select EMIF ADDRESS (8 MSBs) from EMI0CN ...
Page 199
... P4.7 /RD P4.6 ADDR[15:8] P6 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P4.5 /RD P4.6 /WR P4.7 C8051F060/1/2/3/4/5/6/7 Muxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH EMIF WRITE DATA DPL T ALEL T WDS T T ACS Muxed 16-bit READ EMIF ADDRESS (8 MSBs) from DPH DPL T ALEL ...
Page 200
... C8051F060/1/2/3/4/5/6/7 17.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. Figure 17.11. Multiplexed 8-bit MOVX without Bank Select Timing ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P4.5 /WR P4.7 /RD P4.6 ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P4.5 /RD P4.6 /WR P4 ...