HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 23

EVALUATION PLATFORM VIRTEX-5

HW-V5-ML506-UNI-G

Manufacturer Part Number
HW-V5-ML506-UNI-G
Description
EVALUATION PLATFORM VIRTEX-5
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Type
DSPr
Datasheet

Specifications of HW-V5-ML506-UNI-G

Contents
Evaluation Platform, DVI Adapter and CompactFlash Card
Silicon Manufacturer
Xilinx
Features
JTAG Programming Interface, Platform Flash, External Clocking
Kit Contents
Board, Cable, PSU, CD, Docs
Silicon Family Name
Virtex-5
Silicon Core Number
XC5VSX50TFFG1136
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
XC5VSX50TFFG1136
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HW-V5-ML506-UNI-G
Manufacturer:
XILINX
0
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
R
Single-Ended Expansion I/O Connectors
Table 1-9: Expansion I/O Differential Connections (J4)
Header J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits the
signals on this connector to carry high-speed, single-ended data. All single-ended signals
on connector J6 are matched length traces. The V
3.3V by setting jumper J20.
expansion I/O connector.
Table 1-10: Expansion I/O Single-Ended Connections (J6)
J4 Differential Pin Pair
Pos
12
16
20
24
32
36
40
44
48
52
56
60
64
28
4
8
J6 Pin
10
12
14
16
2
4
6
8
Neg
10
14
18
22
26
30
34
38
42
46
50
54
58
62
2
6
Schematic Net Name
www.xilinx.com
Table 1-10
HDR1_10
HDR1_12
HDR1_14
HDR1_16
HDR1_2
HDR1_4
HDR1_6
HDR1_8
HDR2_12
HDR2_16
HDR2_20
HDR2_24
HDR2_28
HDR2_32
HDR2_36
HDR2_40
HDR2_44
HDR2_48
HDR2_52
HDR2_56
HDR2_60
HDR2_64
HDR2_4
HDR2_8
Schematic Net Name
Pos
summarizes the single-ended connections on this
HDR2_10
HDR2_14
HDR2_18
HDR2_22
HDR2_26
HDR2_30
HDR2_34
HDR2_38
HDR2_42
HDR2_46
HDR2_50
HDR2_54
HDR2_58
HDR2_62
HDR2_2
HDR2_6
CCIO
Neg
of these signals can be set to 2.5V or
FPGA Pin
H33
H34
G33
G32
H32
F34
J32
J34
AN32
AC34
AC32
AC33
AF34
AF33
W34
Pos
U33
U32
K33
R33
V32
Y33
L34
P32
T33
Detailed Description
FPGA Pin
AA33
AD34
AE34
AE33
AB32
AB33
AP32
Neg
N32
K34
K32
R34
R32
U31
V33
V34
T34
23

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