HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 26

• Manufacturer Part Number: HW-V5-ML506-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr
• Type: DSPr

Specifications of HW-V5-ML506-UNI-G

• Contents: Evaluation Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: JTAG Programming Interface, Platform Flash, External Clocking
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VSX50TFFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VSX50TFFG1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 1: ML505/ML506/ML507 Evaluation Platform
26
11. Stereo AC97 Audio Codec
Table 1-11: Additional Expansion I/O Connections (J5) (Cont’d)
The ML50x board has an AC97 audio codec (U22) to permit audio processing. The Analog
Devices AD1981 Audio Codec supports stereo 16-bit audio with up to 48-kHz sampling.
The sampling rate for record and playback can be different.
Note:
is designed to be asserted at power-on or at system reset.
Separate audio jacks are provided for Microphone, Line In, Line Out, and Headphone. All
jacks are stereo except for Microphone. The Headphone jack is driven by the audio codec's
internal 50-mW amplifier. The SPDIF jack supplies digital audio output from the codec.
Table 1-12
Table 1-12: Audio Jacks
Table 1-13
Table 1-13: Audio Codec Control Connections
AUDIO_BIT_CLK
AUDIO_SDATA_IN
AUDIO_SDATA_OUT
AUDIO_SYNC
FLASH_AUDIO_RESET_B
Reference Designator
The reset for the AC97 codec is shared with the reset signal for the flash memory chips and
J5 Pin
Net Name
26
27
28
29
30
31
32
summarizes the audio jacks.
shows the control pins for the AC 97 audio codec.
P10
P12
P13
P14
P11
GPIOLED 1
GPIOLED 2
GPIOLED 4
NC
NC
IIC_SCL_EXP
IIC_SDA_EXP
www.xilinx.com
Label
Analog Line - Out
Headphone - Out
Analog Line - In
Microphone - In
SPDIF - Out
FPGA Pin
Function
AG16
AG17
AF18
AE18
AF19
FPGA Pin
ML505/ML506/ML507 Evaluation Platform
G15
G16
L18
F9
F8
-
-
UG347 (v3.1.1) October 7, 2009
GPIO LED 1
GPIO LED 2
GPIO LED 4
Not Connected
Not Connected
Expansion IIC SCL
Expansion IIC SDA
Description
R