HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 36

• Manufacturer Part Number: HW-V5-ML506-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr
• Type: DSPr

Specifications of HW-V5-ML506-UNI-G

• Contents: Evaluation Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: JTAG Programming Interface, Platform Flash, External Clocking
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VSX50TFFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VSX50TFFG1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 1: ML505/ML506/ML507 Evaluation Platform
36
32. Encryption Key Battery
33. SPI Flash
Configuration Address [2:0] allows the user to select among multiple configuration
images. For System ACE configuration, up to eight possible configurations can be stored
on a CF card. The Platform Flash PROM and Linear Flash can hold up to four separate
bitstreams that can be chosen by Configuration Address [2:0].
Mode[2:0] selects the FPGA configuration mode according to
Table 1-18: Configuration Mode DIP Switch Settings
An onboard rechargeable lithium battery is connected to the V
hold the encryption key for the FPGA.
The ML50x board has a 32-Mb SPI Flash (ST Microelectronics M25P32). The SPI Flash can
be used for FPGA configuration or to hold user data. The SPI Flash can be in-system
programmed using a Xilinx download cable with flying leads attached to header J2
(Figure
Mode[2:0]
000
001
010
011
100
101
110
111
1-6).
Master Serial (Platform Flash PROM, up to four configurations)
SPI (One configuration)
BPI Up (Parallel NOR Flash, up to four configurations)
BPI Down (Parallel NOR Flash, up to four configurations)
Master SelectMAP (Platform Flash PROM, up to four configurations)
JTAG (PC4, System ACE up to eight configurations)
Slave SelectMAP (Platform Flash PROM, up to four configurations)
Slave Serial (Platform Flash PROM, up to four configurations)
Figure 1-6: J2 SPI Flash Programming Header
www.xilinx.com
SPI Prog
1
J2
UG347_09_021407
INIT
TMS
TDI
TDO
TCK
GND
VCC3V3
ML505/ML506/ML507 Evaluation Platform
Mode
UG347 (v3.1.1) October 7, 2009
Table
BATT
1-18.
pin of the FPGA to
R