HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 50

• Manufacturer Part Number: HW-V5-ML506-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr
• Type: DSPr

Specifications of HW-V5-ML506-UNI-G

• Contents: Evaluation Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: JTAG Programming Interface, Platform Flash, External Clocking
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VSX50TFFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VSX50TFFG1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 1: ML505/ML506/ML507 Evaluation Platform
50
made as the AUX channels are also used as general-purpose I/O on the XGI connectors
(see
still available for use with the System Monitor functions, but they will not attain the
performance level of the dedicated analog input as noted in the Virtex-5 FPGA System
Monitor User Guide. Access to the dedicated analog input pairs (VP/VN) is provided
through pins 9 and 10 of the System Monitor Header (J9). See
The Virtex-5 FPGA System Monitor function is built around a 10-bit, 200-kSPS
(kilosamples per second) Analog-to-Digital Converter (ADC). When combined with a
number of on-chip sensors, the ADC is used to measure FPGA physical operating
parameters like on-chip power supply voltages and die temperatures. Access to external
voltages is provided through a dedicated analog-input pair (VP/VN) and 16 user
selectable analog inputs, known as auxiliary analog inputs (VAUXP[15:0], VAUXN[15:0]).
The System Monitor is fully functional on power up, and measurement data can be
accessed via the JTAG port pre-configuration. The Xilinx ChipScope™ Pro tool
provides access to the System Monitor over the JTAG port. The System Monitor control
logic implements some common monitoring features. For example, an automatic channel
sequencer allows a user-defined selection of parameters to be automatically monitored,
and user-programmable averaging is enabled to ensure robust noise-free measurements.
The System Monitor also provides user-programmable alarm thresholds for the on-chip
sensors. Thus, if an on-chip monitored parameter moves outside the user-specified
operating range, an alarm logic output becomes active. In addition to monitoring the on-
chip temperature for user-defined applications, the System Monitor issues a special alarm
called Over-Temperature (OT) if the FPGA temperature becomes critical (> 125°C). The
over-temperature signal is deactivated when the device temperature falls below a user-
specified lower limit. If the FPGA power-down feature is enabled, the FPGA enters power
down when the OT signal becomes active. The FPGA powers up again when the alarm is
deactivated.
For additional information about the System Monitor, see
http://www.xilinx.com/systemmonitor
User Guide
Table 1-34: System Monitor Connections
VN
VP
VAUXN[0]
VAUXP[0]
VAUXN[1]
VAUXP[1]
VAUXN[2]
VAUXP[2]
VAUXN[3]
VAUXP[3]
VAUXN[4]
VAUXP[4]
External Input
“10. XGI Expansion Headers,” page 22
[Ref
14].
Table 1-34
FPGA Pin
AC33
AC32
AD34
AC34
AE34
AE33
AB33
AB32
AF34
AF33
U18
V17
www.xilinx.com
shows the System Monitor connections.
Header Pin
and consult the Virtex-5 FPGA System Monitor
J9-10
J4-42
J4-44
J4-46
J4-48
J4-58
J4-60
J4-54
J4-56
J4-50
J4-52
J9-9
for additional details). The AUX channels are
ML505/ML506/ML507 Evaluation Platform
Schematic Net Name
HDR2_42_SM_14_N
HDR2_46_SM_12_N
HDR2_54_SM_13_N
HDR2_44_SM_14_P
HDR2_48_SM_12_P
HDR2_56_SM_13_P
HDR2_58_SM_4_N
HDR2_50_SM_5_N
HDR2_60_SM_4_P
HDR2_52_SM_5_P
UG347 (v3.1.1) October 7, 2009
Table
FPGA_V_N
FPGA_V_P
1-34.
[Ref 24]
R