HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 53

• Manufacturer Part Number: HW-V5-ML506-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr
• Type: DSPr

Specifications of HW-V5-ML506-UNI-G

• Contents: Evaluation Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: JTAG Programming Interface, Platform Flash, External Clocking
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VSX50TFFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VSX50TFFG1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Configuration Options
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
J1
JTAG (Xilinx Download Cable and System ACE Controller) Configuration
R
Platform Flash Memories
TDI
U4
TDO
The FPGA on the ML50x Evaluation Platform can be configured by the following major
devices:
•
•
•
•
•
The following section provides an overview of the possible ways the FPGA can be
configured.
The FPGA, two Platform Flash PROMs, and CPLD can be configured through the JTAG
port. The JTAG chain of the board is illustrated in
The chain starts at the PC4 connector and goes through the Platform Flash PROMs, the
CPLD, the System ACE controller, the FPGA, and an optional extension of the chain to the
expansion card. Jumper J21 determines if the JTAG chain should be extended to the
expansion card.
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and
software debug. The JTAG chain is also used to program the Platform Flash PROM and the
CPLD.
The PC4 JTAG connection to the JTAG chain allows a host computer to download
bitstreams to the FPGA using the iMPACT software tool. PC4 also allows debug tools such
as the ChipScope Pro Analyzer or a software debugger to access the FPGA.
The System ACE controller can also program the FPGA through the JTAG port. Using an
inserted CompactFlash card, configuration information can be stored and played out to
the FPGA. The System ACE controller supports up to eight configuration images that can
selected using the three configuration address DIP switches. Under FPGA control, the
System ACE chip can be instructed to reconfigure to any of the eight configuration images.
The configuration mode should be set to 101. Jumper J21 should exclude the expansion
card from the JTAG chain, and switch SW3, pin 8 should be ON to use System ACE
configuration. When set correctly, the System ACE controller programs the FPGA upon
power-up if a CompactFlash card is present or whenever a CompactFlash card is inserted.
Xilinx download cable (JTAG)
System ACE controller (JTAG)
Two Platform Flash PROMs
Linear Flash memory
SPI Flash memory
TDI
U5
TDO
Figure 1-9: JTAG Chain
TDI
CPLD
U3
www.xilinx.com
TDO
TSTTDI
TSTDO
System ACE
Controller
U2
CFGTDO
CFGTDI
Figure
TDI
J21
1-9.
FPGA
1
2
3
U1
TDO
Configuration Options
Expansion
TDI
TDO
UG347_08_112706
J5
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