ATAVRONEKIT Atmel, ATAVRONEKIT Datasheet - Page 101

• Manufacturer Part Number: ATAVRONEKIT
• Description: KIT AVR/AVR32 DEBUGGER/PROGRMMR
• Manufacturer: Atmel
• Series: AVR®r
• Type: Debuggerr

Specifications of ATAVRONEKIT

• Contents: Programmer/Debugger
• Processor To Be Evaluated: AVR32
• Data Bus Width: 32 bit
• Interface Type: ISP, JTAG
• Core Architecture: AVR
• Kit Contents: ATAVRONEKIT
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Dev Kit (Dev Tool)
• Rohs Compliant: Yes
• Mcu Supported Families: AVR32 32-bit MCU
• For Use With/related Products: AVR® Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8067M–AVR–09/10
4. ADC gain stage output range is limited to 2.4 V
5. The ADC has up to ±2 LSB inaccuracy
6. TWI, a general address call will match independent of the R/W-bit value
7. TWI, the minimum I
8. Setting HIRES PR bit makes PWM output unavailable
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input volt-
age/ output value transfer function of the ADC. The inaccuracy increases with increasing
voltage reference reaching ±2 LSB with 3V reference.
Problem fix/Workaround
None, the actual ADC resolution will be reduced with up to ±2 LSB.
When the TWI is in Slave mode and a general address call is issued on the bus, the TWI
Slave will get an address match regardless of the R/W-bit (ADDR[0] bit) value in the Slave
Address Register.
Problem fix/Workaround
Use software to check the R/W-bit on general call address match.
When the TWI is in Master Read mode and issuing a Repeated Start on the bus, this will
immediately release the SCL line even if one complete SCL low period has not passed. This
means that the minimum SCL low time in the I
Problem fix/Workaround
If this causes a potential problem in the application, software must ensure that the Repeated
Start is never issued before one SCL low time has passed.
Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM
output for the corresponding Timer/Counters (TCx0 and TCx1) unavailable on the pin.
Problem fix/Workaround
Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is
used.
–
–
–
–
–
–
–
16x
32x
64x
1x
2x
4x
8x
gain:
gain:
gain:
gain:
gain:
gain:
gain:
300
150
2
2.4
1.2
0.6
75
38
C SCL low time could be violated in Master Read mode
V
V
V
mV
mV
mV
mV
2
C specification could be violated.
XMEGA A1
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