ATAVRONEKIT Atmel, ATAVRONEKIT Datasheet - Page 48

KIT AVR/AVR32 DEBUGGER/PROGRMMR

ATAVRONEKIT

Manufacturer Part Number
ATAVRONEKIT
Description
KIT AVR/AVR32 DEBUGGER/PROGRMMR
Manufacturer
Atmel
Series
AVR®r
Type
Debuggerr
Datasheets

Specifications of ATAVRONEKIT

Contents
Programmer/Debugger
Processor To Be Evaluated
AVR32
Data Bus Width
32 bit
Interface Type
ISP, JTAG
Core Architecture
AVR
Kit Contents
ATAVRONEKIT
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Development Tool Type
Hardware / Software - Dev Kit (Dev Tool)
Rohs Compliant
Yes
Mcu Supported Families
AVR32 32-bit MCU
For Use With/related Products
AVR® Devices
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATAVRONEKIT
Manufacturer:
Atmel
Quantity:
135
28.
28.1
28.2
28.3
28.3.1
28.3.2
8067M–AVR–09/10
PDI -
Features
Overview
IEEE 1149.1 (JTAG) Boundary-scan
Boundary-scan Order
Boundary-scan Description Language Files
Program and Debug Interface
The programming and debug facilities are accessed through the JTAG and PDI physical inter-
faces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no
general purpose pins are used. JTAG uses four general purpose pins on PORTB.
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s or third party development tools.
The JTAG physical layer handles the basic low-level serial communication over four I/O lines
named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and
boundary scan.
Table 29-12 on page 55
chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned
out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain,
since these pins constitute the TAP pins when the JTAG is enabled.
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. BSDL files are available for
ATxmega384/256/192/128/64A1 devices.
See
PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
JTAG Interface (IEEE std. 1149.1 compliant)
Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)
Access to the OCD system
Programming of Flash, EEPROM, Fuses and Lock Bits
Table 29-12 on page 55
shows the Scan order between TDI and TDO when the Boundary-scan
for ATxmega384/256/192/128/64A1 Boundary Scan Order.
XMEGA A1
48

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