ATAVRONEKIT Atmel, ATAVRONEKIT Datasheet - Page 60

• Manufacturer Part Number: ATAVRONEKIT
• Description: KIT AVR/AVR32 DEBUGGER/PROGRMMR
• Manufacturer: Atmel
• Series: AVR®r
• Type: Debuggerr

Specifications of ATAVRONEKIT

• Contents: Programmer/Debugger
• Processor To Be Evaluated: AVR32
• Data Bus Width: 32 bit
• Interface Type: ISP, JTAG
• Core Architecture: AVR
• Kit Contents: ATAVRONEKIT
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Dev Kit (Dev Tool)
• Rohs Compliant: Yes
• Mcu Supported Families: AVR32 32-bit MCU
• For Use With/related Products: AVR® Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

31. Instruction Set Summary
8067M–AVR–09/10
Mnemonics
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
ORI
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
MUL
MULS
MULSU
FMUL
FMULS
FMULSU
DES
RJMP
IJMP
EIJMP
JMP
RCALL
ICALL
EICALL
Operands
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Rd
Rd,K
Rd,K
Rd
Rd
Rd
Rd
Rd
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
K
k
k
k
Description
Add without Carry
Add with Carry
Add Immediate to Word
Subtract without Carry
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
Logical AND with Immediate
Logical OR
Logical OR with Immediate
Exclusive OR
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Multiply Unsigned
Multiply Signed
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Data Encryption
Relative Jump
Indirect Jump to (Z)
Extended Indirect Jump to (Z)
Jump
Relative Call Subroutine
Indirect Call to (Z)
Extended Indirect Call to (Z)
Arithmetic and Logic Instructions
Branch Instructions
else if (H = 1) then R15:R0
if (H = 0) then R15:R0
Rd + 1:Rd
PC(21:16)
PC(21:16)
PC(21:16)
PC(21:16)
PC(15:0)
PC(15:0)
PC(15:0)
PC(15:0)
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
Operation
PC
PC
PC
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd + Rr
Rd + Rr + C
Rd + 1:Rd + K
Rd - Rr
Rd - K
Rd - Rr - C
Rd - K - C
Rd + 1:Rd - K
Rd • Rr
Rd • K
Rd v Rr
Rd v K
Rd ⊕ Rr
$FF - Rd
$00 - Rd
Rd v K
Rd • ($FFh - K)
Rd + 1
Rd - 1
Rd • Rd
Rd ⊕ Rd
$FF
Rd x Rr (UU)
Rd x Rr (SS)
Rd x Rr (SU)
Rd x Rr<<1 (UU)
Rd x Rr<<1 (SS)
Rd x Rr<<1 (SU)
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
PC + k + 1
Z,
0
Z,
EIND
k
PC + k + 1
Z,
0
Z,
EIND
XMEGA A1
Flags
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
None
Z,C
Z,C
Z,C
Z,C
Z,C
Z,C
None
None
None
None
None
None
None
#Clocks
2 / 3
2 / 3
1/2
3
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
3
(1)
(1)
(1)
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