TMDSEMU100V2U-20T

Manufacturer Part NumberTMDSEMU100V2U-20T
DescriptionXDS100 USB JTAG EMULATOR
ManufacturerTexas Instruments
TMDSEMU100V2U-20T datasheets
 


Specifications of TMDSEMU100V2U-20T

Core ArchitectureARMIc Product TypeEmulator
FeaturesUSB Bus Powered, No Power Supply, Supports USB 1.X And USB 2.0Lead Free Status / RoHS StatusLead free / RoHS Compliant
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Emulation and Trace Headers
Technical Reference Manual
Literature Number: SPRU655G
February 2003 – Revised May 2010

TMDSEMU100V2U-20T Summary of contents

  • Page 1

    Emulation and Trace Headers Technical Reference Manual Literature Number: SPRU655G February 2003 – Revised May 2010 ...

  • Page 2

    ... Copyright © 2003–2010, Texas Instruments Incorporated SPRU655G – February 2003 – Revised May 2010 ...

  • Page 3

    ... Layout and Route Deviations [Advanced Emulation] Appendix E XDS560T Spice Model Appendix F XDS560 v2 System Trace Modeling Appendix G Finding a Buffer's Output Impedance Appendix H Variable Board Impedance ....................................................................................................... Appendix I Revision History SPRU655G – February 2003 – Revised May 2010 ........................................................................... ........................................................................................... ............................................................................................. ......................................................................................... ............................................................................................ ........................................................................... ...................................................................................... ................................................................................ ........................................................................................... ................................................................................................. ................................................................. ........................................................................................... ...................................................................................... ................................................................ ..................................................... ..................................................................... ............................................................................. ............................................................ ............................................................................................... ............................................................................ ......................................................................... ........................................................................................ Copyright © 2003–2010, Texas Instruments Incorporated ................................................ ........................................ Table of Contents ...

  • Page 4

    ... Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com ....................................... ................ ........................................ ..................................... ............ ............................................ ........ ........................... ...... ....................... ........ ........................................ SPRU655G – February 2003 – Revised May 2010 ...

  • Page 5

    ... EMU Pins Modeled as EMU2 or EMU18 27 Buffer Name Decode andOutput Impedance 28 Recommended Series Termination Resistor Value .................................................................................................... 29 Model_name Example 30 Emulation and Trace Headers Revision History SPRU655G – February 2003 – Revised May 2010 List of Tables ................................................................ ................................................................................ ............................................................................. .......................................................................... ............................................................................. ............................................................................................. ......................................................................... ..................................................................................... ..................................................................... .................................................................... .................................................................................... ..................................................................................... .................................................................................... ............................................................................. ........................................................................................... ................................................................. ................................................................. ......................................................................... ............................................................................... .......................................................................... ................................................................... ....................................................................... Copyright © 2003–2010, Texas Instruments Incorporated .......................................... 31 ....................................... ...

  • Page 6

    ... About This Manual This technical reference describes how to incorporate Texas Instruments' next-generation emulation header on a board with a trace-enabled DSP. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • ...

  • Page 7

    ... TMS320C6000, XDS510, XDS560 are trademarks of Texas Instruments. ARM is a trademark of of ARM Limited in the EU and other countries. SPRU655G – February 2003 – Revised May 2010 Copyright © ...

  • Page 8

    ... EMU pins to an emulator with trace capture support, such as the XDS560T. Texas Instruments device's support various combinations of DSP core trace and system trace. In all cases, the trace data rates require that the EMU pins be treated as high-speed clocks within your design ...

  • Page 9

    ... MIPI 60-Pin TI 60-Pin MIPI 60-Pin TI 20-Pin CTI Appendix summarize the header information. For specific pin assignments, see http://www.samtec.com/ftppub/cpdf/SOLC-MKT.PDF http://www.samtec.com/ftppub/cpdf/SOLC.PDF Copyright © 2003–2010, Texas Instruments Incorporated Fundamental Information Notes Check Availability Check Availability Pin Saver Check Availability Check Availability A ...

  • Page 10

    ... Emulation and Trace Headers 0.8500" Figure 1. TI 60-Pin Emulation Header 0.8375" Figure 2. MIPI 60-Pin Header 0.50" Figure 3. TI 20-Pin CTI Header Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com Table 7 shows a comparison of 0.3200" 0.295" 0.2960" SPRU655G – February 2003 – Revised May 2010 ...

  • Page 11

    ... SPRU655G – February 2003 – Revised May 2010 0.7200" Area (in square inches) 0.2720 in 0.2471 in 0.148 in 0.3451 in 0.2808 in 0.2431 in Table 8. Summary: Header Changes Copyright © 2003–2010, Texas Instruments Incorporated Target Mating Caution 01 0.3100" 01 Notes 2 Includes mounting pads 2 Includes mounting pads 2 Includes mounting pads ...

  • Page 12

    ... Only header type 0000 is currently supported, where 0 is GND and Connect. All other combinations are reserved. Connect to device pin of same name. Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com SPRU655G – February 2003 – Revised May 2010 ...

  • Page 13

    ... Ground pin. Ground pin. Type 1 must be connected to GND. Ground pin. Ground pin. Ground pin. Ground pin. Ground pin. Ground pin. Ground pin. 13. Table 10. Summary: TI 60-Pin Header Pinout Copyright © 2003–2010, Texas Instruments Incorporated Header Pin Assignment 13 Emulation and Trace Headers ...

  • Page 14

    ... TCK TDO TDI Connect to system reset RTCK nTRST nTRST NC NC 13. Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com (1) (2) (3) Notes JTAG IO voltage reference current limited via 100-Ω resistor. May need to be buffered. Open drain output from (3) emulator; use 4.7-KΩ PU. ...

  • Page 15

    ... EMU4 NC EMU5 NC EMU6 NC EMU7 NC EMU8 NC EMU9 NC EMU10 NC EMU11 NC EMU12 NC EMU13 NC EMU14 NC EMU15 NC EMU16 NC EMU17 NC EMU18 Copyright © 2003–2010, Texas Instruments Incorporated Header Pin Assignment (1) (2) (3) (continued) Notes EMU IO voltage reference current limited via 100-Ω resistor. 15 Emulation and Trace Headers ...

  • Page 16

    ... RTCK. If your target device has an RTCK signal, you must connect this signal to RTCK on the emulator header. May need to be buffered. Open drain output from emulator, use 4.7-KΩ PU. 13. Table 13. Summary: Header Pin Assignments Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com (1) (2) (3) (continued) Notes (2) (2) SPRU655G – ...

  • Page 17

    ... XDS560 v2 System Trace emulator. The XDS560T does not support this feature. Figure top view of Texas Instruments' 60-pin emulation header, illustrating the orientation and pin location of the 60-pin emulation header. For specific pin assignments, see emulation and debug pod incorporates a pin 1 (red dot) locator on the emulation and debug pod (Figure 7) ...

  • Page 18

    ... Edge of Board Figure 7. Emulator Cable Connector Superimposed Over 60-Pin Header 18 Emulation and Trace Headers Side 1 Location on emulation header Pin 1 Location on emulation pod (red dot) Towards device Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com SPRU655G – February 2003 – Revised May 2010 ...

  • Page 19

    ... Note: Pin 6 may need to be cut to mate with the emulator's target cable. Figure 9. TI 20-Pin CTI Header Pin Location SPRU655G – February 2003 – Revised May 2010 edge Copyright © 2003–2010, Texas Instruments Incorporated Header Pin Assignment Towards device Emulation and Trace Headers 19 ...

  • Page 20

    ... Pull-up within device per device data sheet In Pull-up within device per device data sheet In Pull-down within device per device data sheet Figure 10 Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com shows the basic connection for SPRU655G – February 2003 – Revised May 2010 ...

  • Page 21

    ... The EMU and TDO series termination Table 11. Table 11 for notes on nTRST and nTRST_PD use. Guide. If you decide pull-ups are needed on EMU0 and EMU1 keep the Guide. Copyright © 2003–2010, Texas Instruments Incorporated Electrical Requirements (B) Emulation Header / (F) (G) Emulation and Trace Headers ...

  • Page 22

    ... Figure 27; and if there is a direct connection to the device's Figure 28. Figure 29). To determine the proper termination resistor value Cable Device_Output Termination_Resistor . Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com - determine the Device_Output Termination_Resistor - Cable (Figure 26). (Figure 27). Values should Cable ...

  • Page 23

    ... Table 19. Table 19. General Specifications Section 8 and Section 9. Figure 16; for the MIPI 60-pin connector clearance, see 17. Figure 11. All percentages listed are with respect to the V Copyright © 2003–2010, Texas Instruments Incorporated Buffering Figure 18 and Figure 20. Figure 19 and Figure 21. High 23 Emulation and Trace Headers ...

  • Page 24

    ... High or a duration less than the fall time of the pulse. High . Table 20. Summary: Acceptable Signals High . High or 165 mV for a 3.3 V signal. Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com High are High are High or less than the rise time of the pulse. ...

  • Page 25

    ... The EMU[2]-EMU[n] terminations are not Section 10. T2 maximum distance ≤ 0.5 " ≤ T3 maximum distance Figure 13) should have symmetrical lengths to the Copyright © 2003–2010, Texas Instruments Incorporated Connecting Alternate Headers 2.5 " 1 60-pin header J2 2.5 " ≤ 14-pin header Emulation and Trace Headers 25 ...

  • Page 26

    ... In both figures the orientation provides for a left side cable entry. 26 Emulation and Trace Headers 0.5" ≤ Figure 13. Symmetrical Nets Figure 14 illustrates the maximum recommended routing Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com Symmetrical lengths Figure 15 shows a MIPI 60-pin SPRU655G – February 2003 – Revised May 2010 ...

  • Page 27

    ... EMU pin from the connector. C12 D13 C13 D14 C14 D15 C15 3" maximum trace length Red highlighted pin is the farthest 11 9 EMU pin from the connector Copyright © 2003–2010, Texas Instruments Incorporated Layout and Routing Requirements 27 Emulation and Trace Headers ...

  • Page 28

    ... Emulation and Trace Headers illustrate the recommended header distance from the target processor. provide models representing the XDS560T and XDS560 v2 System Trace Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com Section 18), the maximum ) for a net class (grouping of pd SPRU655G – ...

  • Page 29

    ... SPRU655G – February 2003 – Revised May 2010 Traditional JTAG Emulation Layout and Route Distance Deviations illustrate the recommended header distance from the target processor. for the MIPI 60-pin cable. Deviations from the recommended route " Copyright © 2003–2010, Texas Instruments Incorporated Appendix E for 0.556" 29 ...

  • Page 30

    ... Emulation and Trace Headers 1.230" 0.775" 20). Given the connector housing is 0.274" off of the plane of the board, Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com 0.725" 1.060" 1.075" 1.175" SPRU655G – February 2003 – Revised May 2010 ...

  • Page 31

    ... Keep-out area 0.3200" 0.1330" 0.5800" 0.8800" 0.4200" 21). Given the cable's adapter board is 0.292" off of the plane of the Keep-out area 0.295² 1.128² Copyright © 2003–2010, Texas Instruments Incorporated 0.4500² 0.8500" 0.300² 0.8375² Emulation and Trace Headers 31 ...

  • Page 32

    ... RTCK, see 32 Emulation and Trace Headers do not show RTCK. The header's RTCK signal must be connected on Section 8, Header Pin Assignment. For multiprocessor configurations that Table 13 note 2. Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com SPRU655G – February 2003 – Revised May 2010 ...

  • Page 33

    ... JTAG signals between processors. The same 30-device restriction also applies to this configuration. SPRU655G – February 2003 – Revised May 2010 TDI-TDO DSP1 Copyright © 2003–2010, Texas Instruments Incorporated Multiple Device Considerations TDI-TDO EMU0 EMU1 ...

  • Page 34

    ... Synchronous TCK, TMS, TDO TRST EMU0:n TDI DSP1 (Section 10 and Section Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com TDI-TDO EMU0:1 TCK, TMS, TRST DSPn DSP3 Section 10. TCK, TMS, ...

  • Page 35

    ... SPRU655G – February 2003 – Revised May 2010 Figure 25), you may connect each EMU pin used for 2.25" 0.50" Figure 25. Parallel Termination 2 Processors 3 Processors Copyright © 2003–2010, Texas Instruments Incorporated Multiple Device Considerations Emulation Header 4 Processors Emulation and Trace Headers ...

  • Page 36

    ... This chart assumes 4.1, which is typical for FR-4 material. This appendix also shows how to design a multiple impedance printed circuit board. 36 Alternate Target Impedance Configurations Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com SPRU655G – February 2003 – Revised May 2010 ...

  • Page 37

    ... W 1” 3.0" max 22 W 1" max ( Cable Device_Output Section Buffering - Methods, Techniques and Terminations Copyright © 2003–2010, Texas Instruments Incorporated 0.5" Emulation header TCK Emulation header TCK Emulation header TCK Emulation header TCKRTN/RTCK = Z . The series Termination_Resistor 10 ...

  • Page 38

    ... The distance for this node under all conditions cannot exceed 1.0". 38 Buffering - Methods, Techniques and Terminations 0.5" 2.5" Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com Section 10. Emulation header ...

  • Page 39

    ... V IO 74LVC1G32 10k 100 8 74LVC1G32 10k 100 W 8.2 pF Section 10 and Appendix Copyright © 2003–2010, Texas Instruments Incorporated TCK 0.5" (TI 60-pin or MIPI 60-pin header) ( 10k W TI 60-pin (A) header (pin A1, GND) or MIPI 60-pin (A) header (pin 16, GND) 0.5" TCK (TI 14-pin or TI 20-pin CTI header) ...

  • Page 40

    ... The distance for this node under all conditions cannot exceed 3" 14-Pin and 60-Pin Headers in Parallel 2.5" 0.5" 2.5" Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com 14-pin header 60-pin header SPRU655G – February 2003 – Revised May 2010 ...

  • Page 41

    ... The recommended header distance from the target processor is 3 inches maximum. Models representing the target interconnect are provided in and XDS560 v2 System Trace emulators. SPRU655G – February 2003 – Revised May 2010 Appendix E Copyright © 2003–2010, Texas Instruments Incorporated and Appendix F for the XDS560T 41 ...

  • Page 42

    ... This illustration references a 50-Ω Figure 39 and Example 5 using TI's XDS560T and a 50-Ω character Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com using TI's XDS560T and a using TI's XDS560T and a using TI's XDS560T and a SPRU655G – February 2003 – Revised May 2010 ...

  • Page 43

    ... K C50 3.9 p U40 (Comparator) Tran10 0.7” R100 100 K ESD 3p C13 termination ESD diode Copyright © 2003–2010, Texas Instruments Incorporated Appendix E DSP output 60-pin header input LVDS Trace Cable Via assembly Tran4 Tran3 0.576” 5.625” ...

  • Page 44

    ... R214 InputLVDS 0 1.5K R8 InputLVDS 0 100K ***** Spice models and macro models ***** ***** End of spice models and macro models ***** .tran 1n 100n 0.0 1n .save all .end 44 XDS560T Spice Model Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com SPRU655G – February 2003 – Revised May 2010 ...

  • Page 45

    ... The result of your 50-Ω target PCB simulation and modeling should be an acceptable waveform, similar to that illustrated in Figure 33. Figure 33. EMU0 Acceptable Wave Form (Host Side, TI's XDS560T Pod - 50 Ω) SPRU655G – February 2003 – Revised May 2010 Copyright © 2003–2010, Texas Instruments Incorporated Appendix E 45 XDS560T Spice Model ...

  • Page 46

    ... R214 InputLVDS 0 1.5K R8 InputLVDS 0 100K ***** Spice models and macro models ***** ***** End of spice models and macro models ***** .tran 1n 100n 0.0 1n .save all .end 46 XDS560T Spice Model Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com SPRU655G – February 2003 – Revised May 2010 ...

  • Page 47

    ... The result of your 75-Ω target PCB simulation and modeling from waveform illustrated in Figure Figure 34. EMU0 Wave Form (Host Side, TI's XDS560T - 75 Ω) SPRU655G – February 2003 – Revised May 2010 34. Copyright © 2003–2010, Texas Instruments Incorporated Appendix E Example 2 should be similar to the XDS560T Spice Model 47 ...

  • Page 48

    ... C52 Via 3.9 p Tran6 1.5 K 2.87 K 0.6” R229 R228 ESD for termination Termination Via Model) Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com Cable Trace assembly Tran4 Tran3 1.10” 5.625” Via Trace-via ESD diode Via Tran5 1.4” ...

  • Page 49

    ... Spice models and macro models ***** ***** End of spice models and macro models ***** .tran 10p 100n 0.0 5p .save all .end SPRU655G – February 2003 – Revised May 2010 Copyright © 2003–2010, Texas Instruments Incorporated Appendix E Figure 35 for a 50-Ω target 49 XDS560T Spice Model ...

  • Page 50

    ... Figure 36. EMU2 Type Signals Acceptable Wave Form (Host Side, TI's XDS560T Pod - 50 Ω) 50 XDS560T Spice Model Figure 36. Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com Example 3 should be an acceptable SPRU655G – February 2003 – Revised May 2010 ...

  • Page 51

    ... K R310 C20 Via 3.9 p 1.5 K 2.87 K R307 R309 Termination 0.5 p C10 Via ESD diode Model) Copyright © 2003–2010, Texas Instruments Incorporated Appendix E Pod header Cable Trace Via assembly Tran4 Tran3 0.40” 5.625” C4 0.5 p Via Tran5 Tran6 0.2” ...

  • Page 52

    ... Spice models and macro models ***** ***** End of spice models and macro models ***** .tran 2n 100n 0.0 2n .save all .end 52 XDS560T Spice Model Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com Figure 37 for a 50-Ω target SPRU655G – February 2003 – Revised May 2010 ...

  • Page 53

    ... Figure 38. EMU18 Type Signals - Acceptable Wave Form (Host Side, TI's XDS560T Pod - 50 Ω) SPRU655G – February 2003 – Revised May 2010 Figure 38. Copyright © 2003–2010, Texas Instruments Incorporated Appendix E Figure 37 should be an acceptable XDS560T Spice Model ...

  • Page 54

    ... 100 K 0.7” Tran7 ESD R100 100 K termination C13 3 p ESD diode Model) Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com Probe points DSP signal output 14-pin header input to LVDS R300 Pod header 100 K Cable Trace Via assembly Tran4 Tran3 0.576” ...

  • Page 55

    ... Spice models and macro models ***** ***** End of spice models and macro models ***** .tran 1n 100n 0.0 1n .save all .end SPRU655G – February 2003 – Revised May 2010 Copyright © 2003–2010, Texas Instruments Incorporated Appendix E Figure 39 for a 50-Ω 55 XDS560T Spice Model ...

  • Page 56

    ... The result of your 50-Ω dual-header target PCB simulation and modeling from acceptable waveform, similar to that illustrated in Figure 40. EMU0 Dual-Header - Wave Form (Host Side, TI's XDS560T Pod - 50 Ω) 56 XDS560T Spice Model Figure 40. Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com Figure 39 should be an SPRU655G – February 2003 – Revised May 2010 ...

  • Page 57

    ... For the most accurate simulation, TI recommends using tools that support simulation with IBIS models of your target device (U11.1 in Figure 41) and the AVC4T245_RGY buffer. SPRU655G – February 2003 – Revised May 2010 Copyright © 2003–2010, Texas Instruments Incorporated 57 XDS560 v2 System Trace Modeling ...

  • Page 58

    ... Bott... 47.6 ohms 50.4 ohms 48.6 ohms 59.510 ps 7.449 ps 183.094 ps SLM_qth01_qsh0... 0.050 in 1.057 in TRCLK0 TRCLK0 Figure 41. TRCLK[0] Model Schematic Copyright © 2003–2010, Texas Instruments Incorporated VCC_TR... 1.8V TL5 R49 50.4 ohms 100.0 K ohms 4.462 ps 0.030 in TRCLK0 ML1 U9.13 TL2 R79 TL1 Bott ...

  • Page 59

    ... Nominal impedance; i.e., 25 Ω. Buffer's design frequency; i.e., 250 MHz MHz B = 100 MHz C = 150 MHz D = 200 MHz E = 250 MHz F = 300 MHz Output Impedance (2) Copyright © 2003–2010, Texas Instruments Incorporated to decode the name and Recommended Termination Resistor Finding a Buffer's Output Impedance 59 ...

  • Page 60

    ... EPUFZSCP18 2.72E-01 EPUFZSCP18 8.00E-01 EPUFZSCP18 4.11E-01 EPUFZSCP18 9.35E-01 EPUFZSCP18 6.07E-01 EPUFZSCP18 6.51E-01 EPUFZSCP18 4.39E-01 EPUFZSCP18 1.61E-01 Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com L_pin C_pin 2.78E-09 1.62E-12 2.58E-09 1.66E-12 2.67E-09 1.47E-12 2.34E-09 1.52E-12 2.62E-09 1.41E-12 2.62E-09 1.49E-12 2.47E-09 1.58E-12 2 ...

  • Page 61

    ... If h=7 mils, and mils, a 7.5-mil wide trace has a 50- impedance and a 3.5-mil wide 5 mil trace has a 71- impedance. 7 mil b 5 mil 7 mil 5 mil Copyright © 2003–2010, Texas Instruments Incorporated 3 mil 4 mil 5 mil 6 mil 7 mil 8 mil 9 mil 10 mil 11 mil 12 mil ...

  • Page 62

    ... This revision history highlights the technical changes made to the document in revision D. Table 30. Emulation and Trace Headers Revision History See Additions/Modifications/Deletions Table 12 Added Footnote (1) to TDIS signal 62 Revision History Copyright © 2003–2010, Texas Instruments Incorporated www.ti.com SPRU655G – February 2003 – Revised May 2010 ...

  • Page 63

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...