ATDS1140PC

Manufacturer Part NumberATDS1140PC
DescriptionATMEL SYNARIO VHDL SYNTHESIS OPT
ManufacturerAtmel
TypePC-Based
ATDS1140PC datasheet
 

Specifications of ATDS1140PC

For Use With/related ProductsATF15xx-DK2Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Features
Comprehensive CPLD/PLD Design Environment
User-friendly Microsoft Windows™ Interface (Win 95, Win 98, Win NT)
Powerful Project Navigator
– Utilizes Intelligent Device Fitters for Automatic Logic Synthesis and
Device Resource Assignment
– Allows Design Specification with Schematic Entry or the ABEL-HDL
Integrated ABEL Text Design Entry and Synthesis
– Friendly Windows-based User Interface is Easy to Learn and Use
– ABEL-HDL Design Entry Provides Detailed Support for
Programmable Logic Devices
– Full Hierarchical Support Makes Large Designs Easier to Manage; Large
All-behavioral Designs can be Created without Drawing any Schematics
Integrated Verilog™ Timing Simulator (Optional)
– Fast, Functional Simulation is Performed Directly from the Schematic
or Behavioral Source File, Providing Quick Feedback on Logic Errors
as the Design is Entered
– Full Timing Simulation with Delay-annotated Models Provides
Comprehensive Support for Timing Problems in Routed Devices
– Logic-analyzer-like Waveform Viewer Provides Flexible Results Viewing,
and Updates Every Time you Single-step the Simulator
– Cross-probing Capabilities between the Schematic and Waveform Viewer Tie
Simulation Results Directly Back to the Source Design, Making Results
Easier to Interpret
– Interactive Debugging Provides Force/Preset/Monitor Access to all of the Design’s
Signals, for Fast and Easy, On-the-fly Changes
– Industry-standard Verilog HDL Simulation Language Ensures Timely
Support for New Device Architectures
IEEE 1076 VHDL Synthesis and Simulation (Optional)
Description
Atmel-Synario is an integrated CPLD/PLD design tool. It supports all proprietary, and
JEDEC standard devices offered by Atmel. The usual CAE tool capability is combined
with CPLD specific functionality. A tightly integrated Windows environment gives the
user a friendly, and powerful interface. The system combines schematic and behav-
ioral entry methods. Functional and timing simulation are also supported. An
intelligent design manager, supervises file manipulation and controls the design flow.
This function allows a user to move quickly from one design to another and evaluate
different implementations for an optimal solution.
Atmel-Synario
CPLD/PLD
Design
Software
ATDS1100PC
ATDS1120PC
ATDS1130PC
ATDS1140PC
Rev. 0714C–09/99
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ATDS1140PC Summary of contents

  • Page 1

    ... Functional and timing simulation are also supported. An intelligent design manager, supervises file manipulation and controls the design flow. This function allows a user to move quickly from one design to another and evaluate different implementations for an optimal solution. Atmel-Synario CPLD/PLD Design Software ATDS1100PC ATDS1120PC ATDS1130PC ATDS1140PC Rev. 0714C–09/99 1 ...

  • Page 2

    ... Project Navigator Atmel-Synario Project Navigator is the core of the system powerful and simple design flow controller. Built-in intelligence, gives file and run option knowledge for each device. Select the ATF1500 and all the steps required to design, simulate, compile and fit will appear. Change to ATF22V10 and the steps change accordingly ...

  • Page 3

    ... You can build device-independent soft macros the same way. If you desire architecture specific functions, simply use the Atmel-Specific library for more efficient utilization. Now going from ATF16V8C to a high-density ATF1508 CPLD is only a compilation away. ...

  • Page 4

    ... ABEL Integration into Atmel-Synario: Behavioral Entry and Simulation ABEL is one of the tools integrated into Atmel-Synario. Therefore, importing existing PLD designs into a larger designs is straight forward. Adding new logic, and reimple- menting into a larger CPLD is simple. Experienced ABEL users can get started using Synario ABEL tool, then gradu- ally use more of the extended Atmel-Synario capability ...

  • Page 5

    ... Verilog – Functional and Timing Simulation Option Verilog simulation is another of the Atmel-Synario tools. This standard simulation package gives functional and full timing simulation. The simulation package is fully compati- ble with Open-Verilog, which allows construction of powerful test benches and result analysis and summary functions. Atmel-Synario Simulation creates simulation models directly from Synario’ ...

  • Page 6

    Waveform Editor/Viewer Fast simulation analysis and debug are at your fingertips with waveform editor. The powerful waveform editor enables simple stimulus generation, and easy result Peak VHDL – Simulator Option The Accolade Peak VHDL professional edition simulator is a powerful, ...

  • Page 7

    ... Ordering Information Part Number System ATDS1100PC Atmel-Synario Basic ATDS1120PC Atmel-Synario Verilog Simulation (Option) ATDS1130PC Atmel-Synario VHDL Synthesis (Option) ATDS1140PC Atmel-Synario VHDL Simulation (Option) System Requirements Environment Windows (95 NT) RAM 16MB Hard Disk 80MB Processor Intel or compatible Parallel Port Microsoft Mouse or compatible ...

  • Page 8

    ... No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...