ATDS1140PC Atmel, ATDS1140PC Datasheet - Page 5

• Manufacturer Part Number: ATDS1140PC
• Description: ATMEL SYNARIO VHDL SYNTHESIS OPT
• Manufacturer: Atmel
• Type: PC-Basedr

Specifications of ATDS1140PC

• For Use With/related Products: ATF15xx-DK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Verilog – Functional and Timing Simulation Option
Verilog simulation is another of the Atmel-Synario tools.
This standard simulation package gives functional and full
timing simulation. The simulation package is fully compati-
ble with Open-Verilog, which allows construction of
powerful test benches and result analysis and summary
functions. Atmel-Synario Simulation creates simulation
models directly from Synario’s source files. This, coupled
with an extremely fast simulator, quickly tells you whether
your logic is correct while you’re entering it – even before
the synthesis and fitting steps. After fitting to a specific
device, the user may verify the desired timing. Solve tough
timing problems with full delay-annotated simulation mod-
els created by the fitter.
Atmel-Synario Simulator doesn’t need architecture specific
libraries and models. Simply identify which portion of the
design you want to simulate and the stimulus you want
Note:
Cross-probing between the schematic and waveform viewer ties simulation results directly back to the source for faster and
easier interpretation. Results update each time you single-step the simulator.
ATDS1100PC/1120PC/1130PC/1140PC
applied. Then press “go”. In batch mode, you can start and
stop simulation from the control panel. Or you can explore
your circuit’s functionality interactively. Verilog language
support also assures timely device support.
The Verilog simulation option includes a waveform viewer
display that resembles a logic analyzer format. The wave-
form viewer updates whenever you simulate, even after
each step of single-step session. Once a simulation runs,
the values at the cursor in the waveform viewer are
“dynamically backnotated” into the schematic. This allows
you to debug your hierarchical design by viewing the logic
values of the buried nets in the schematic as you move the
cursor in the waveform viewer. To view a new signal, just
“probe” the new in the schematic and the signal will appear
in the waveform viewer.
Multiple entry methods:
• Use the best one fir the application
• Mix methods for efficient design
• Quick translation of existing designs
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