ATAVRSB100 Atmel, ATAVRSB100 Datasheet - Page 11

• Manufacturer Part Number: ATAVRSB100
• Description: SMART BATTERY DEVELOPMENT KIT
• Manufacturer: Atmel
• Type: Smart Batteryr

Specifications of ATAVRSB100

• Contents: Fully Assembled Evaluation Board
• Processor: ATmega406
• Processor To Be Evaluated: ATmega406
• Data Bus Width: 8 bit
• Interface Type: JTAG
• For Use With/related Products: ATmega406
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2367281

2.3.4 Coulomb Counter and current measurement
2.3.5 Battery protection circuits/built-in hardware
2.4 Cell voltage simulator
2598C-AVR-06/06
the cells. Correspondingly, the Charge (and optional Precharge) FET must be
positioned at the pack’s main terminals. The BATT pin is therefore used to provide
the high-side power supply to the Charge and Precharge FET drivers, since the BATT
pin must be connected on the host/charger side of the circuit.
The Charge and Discharge FETs must be able to handle the maximum current
produced or absorbed by the pack. As such, attention must be paid to their
characteristics, particularly their power dissipation and current capability. The
Precharge FET handles much lower current than the Charge FET, and therefore is
not as critical. (This is also the reason that a low-cost FET with relatively high RdsON
can be used) The Discharge FET is implemented as a separate P-channel device to
allow it to dissipate power at the same time as the Charge FET, since they typically
are on at the same time.
Assuming a current of 4A to be an appropriate maximum, the power dissipation of a
60mΩ FET will be 240mW. With a typical SO-8 package device used as the
Discharge FET, this will yield a die temperature increase of about 12°C over ambient,
which is quite acceptable. For the Charge and Precharge FETs, a dual device can be
used. With an on-resistance of 35mΩ, a 4A current will yield a dissipation of 140mW
in the TSSOP-8 package, with a resulting die temperature increase above ambient of
17.5°C, which is also an acceptable figure.
The PI and NI pins are the input to the Coulomb Counter ADC. Since this is a very
high sensitivity input, care has been taken in the layout to ensure that leakage from
other voltage sources is minimized. The layout of the ATAVRSB100 board includes
GND traces, which act as leakage absorbers. It is highly recommended to not use
No-Clean flux when manufacturing production boards, as such leaves a residue that
may be conductive. As with all differential inputs, the same resistance value should
be used for both sides of the input filter.
For best results, the sense resistor and the input filter circuitry are grouped tightly and
placed as close to the ATmega406 device as possible.
The PPI and NNI inputs receive the voltage from the sense resistor unfiltered. This
allows for quick response to short-circuit situations. No capacitance should be added
to these pins. The input resistors here should also be the same value, as is standard
practice on differential inputs. Increasing the value of these resistors above 1K should
be avoided.
The PVT pin serves as the Deep Under-voltage sense input.
The ATAVRSB100 includes circuitry to accurately simulate cell voltages. Wiring
details for V-SIM are shown on the SB100 board, near CONN2 pin 1. When using V-
SIM mode, ensure that no external power is connected to the B+ and B- terminals on
CONN1.
A constant current source supplies a series chain of four potentiometers. Since the
current is regulated, adjusting any one of the potentiometers results only in a
corresponding change in voltage across that potentiometer; the voltage across the
others is not affected. (These signals are buffered before being presented to the
CELLx inputs, and can be seen directly by measuring on the appropriate terminals of
AVR454
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