AD6600ST/PCB Analog Devices Inc, AD6600ST/PCB Datasheet

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AD6600ST/PCB

Manufacturer Part Number
AD6600ST/PCB
Description
BOARD EVAL ADC RSSI W/AD6600AST
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6600ST/PCB

Rohs Status
RoHS non-compliant
a
PRODUCT DESCRIPTION
The AD6600 mixed-signal receiver chip directly samples signals
at analog input frequencies up to 250 MHz. The device includes
AIN
AIN
BIN
BIN
DETECT
PEAK
0dB, –12dB, –24dB
0dB, –12dB, –24dB
A_SEL
RSSI
ATTEN
ATTEN
SET
B_SEL
3
GAIN
GAIN
RSSI
FUNCTIONAL BLOCK DIAGRAM
SELECT GAIN
+12, +18dB
AVCC
GAIN
AD6600
FLT
GND
NOISE FILTER
two input channels, each with 1 GHz input amplifiers and
30 dB of automatic gain-ranging circuitry. Both channels are
sampled with a 450 MHz track-and-hold followed by an 11-bit,
20 MSPS analog-to-digital converter. Digital RSSI outputs, an
A/B channel indicator, a 2× Clock output, references, and con-
trol circuitry are all on-chip. Digital output signals are two’s
complement, CMOS-compatible and interface directly to
3.3 V or 5 V digital processing chips.
The primary use for the dual analog input structure is sampling
both antennas in a two-antenna diversity receiver. However,
Channels A and B may also be used to sample two independent
IF signals. Diversity, or dual-channel mode, is limited to 10 MSPS
per channel. In single-channel mode, the full clock rate of
20 MSPS may be applied to a single carrier.
The AD6600 may be used as a stand-alone sampling chip, or it
may be combined with the AD6620 Digital Receive Signal Pro-
cessor. The AD6620 provides 10 dB–25 dB of additional pro-
cessing gain before passing data to a fixed- or floating-point DSP.
Driving the AD6600 is simplified by using the AD6630 differen-
tial IF amplifier. The AD6630 is easily matched to inexpensive
SAW filters from 70 MHz to 250 MHz.
Designed specifically for cellular/PCS receivers, the AD6600
supports GSM, IS-136, CDMA and Wireless LANs, as well as
proprietary air interfaces used in WLL/fixed-access systems.
Units are available in plastic, surface-mount packages (44-lead
LQFP) and specified over the industrial temperature range
(–40°C to +85°C).
ENCODE
630
ENCODE
Dual Channel, Gain-Ranging
FLT
RESONANT
CONVERTER
PORT
ENC
TIMING
A/D
ENC
11
COMPLEMENT
RSSI
TWO'S
DVCC
3
ADC with RSSI
AB_OUT
D10–D0
RSSI [2:0]
CLK2
AD6600

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AD6600ST/PCB Summary of contents

Page 1

PRODUCT DESCRIPTION The AD6600 mixed-signal receiver chip directly samples signals at analog input frequencies up to 250 MHz. The device includes 0dB, –12dB, –24dB AIN ATTEN AIN DETECT SET PEAK RSSI BIN ATTEN BIN 0dB, –12dB, –24dB A_SEL two ...

Page 2

AD6600–SPECIFICATIONS DC SPECIFICATIONS (AVCC = 5 V, DVCC = 3 Parameter ANALOG INPUTS (AIN, AIN/BIN, BIN) Differential Analog Input Voltage Range Differential Analog Input Resistance Differential Analog Input Capacitance PEAK DETECTOR (Internal), RSSI Resolution RSSI Gain Step 3 ...

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TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS; T Parameter A/D CONVERTER Conversion Rate Maximum Conversion Rate Minimum Conversion Rate Aperture Uncertainty ENCODE INPUTS (ENC, ENC) 2 Period 3 ...

Page 4

AD6600–SPECIFICATIONS TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; T Parameter ENCODE/CLK2× 3 Encode Rising to CLK2× Falling 4 Encode Rising to CLK2× Rising @ ...

Page 5

V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50 SPECIFICATIONS otherwise noted.) Parameter 1 ANALOG INPUTS 2 Analog Input 3 dB Bandwidth Differential Analog Input Voltage Range 70 MHz ...

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AD6600–SPECIFICATIONS AC SPECIFICATIONS (continued) Parameter ANALOG INPUTS (Continued) Signal-to-Noise Ratio (Continued) AIN = 200 MHz @ –1 dBFS @ –6 dBFS @ –10 dBFS @ –12 dBFS to –42 dBFS @ –54 dBFS AIN = 250 MHz @ –1 dBFS ...

Page 7

AC SPECIFICATIONS (continued) Parameter WORST OTHER SPUR (4th or Higher) AIN = 70 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to –42 dBFS AIN = 150 MHz @ –1 dBFS @ –6 dBFS @ –12 dBFS to ...

Page 8

... AVCC V V. Parameter is a typical value only AVCC V Model °C –40 +85 °C 150 AD6600AST °C 300 °C AD6600ST/PCB = 16°C/W, θ = 55°C/W. JA ORDERING GUIDE Temperature Package Package Range Description Option –40°C to 44-Terminal LQFP ST-44 +85°C (Low-Profile Quad (Ambient) Plastic Flatpack) Evaluation Board ...

Page 9

Pin Number Name 1, 33 DVCC 2, 5, 13, 19, 21, 24, 30, 32 GND 14, 15, 18, 20, 25, 31 AVCC 6–8 RSSI[2: B_SEL, A_SEL 11 AIN AIN 12 FLT, FLT 16, 17 BIN ...

Page 10

AD6600 DEFINITIONS OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. The bandwidth is determined by the internal track-and-hold when the ...

Page 11

RSSI Gain Step The input amplitude span between taps of the RSSI (received signal strength) attenuator ladder. Ideally each stage should span input power. RSSI Hysteresis The amount of movement in the RSSI switch points, depending on ...

Page 12

AD6600 EQUIVALENT CIRCUITS ATTENUATOR STAGE AVCC EQUIVALENT INPUT R SHOWN ONLY AIN 100 V REF GND BUF AVCC 100 AIN GND AVCC ISEL_A ISEL_B AVCC A_SEL BIAS GND GND DVCC CURRENT MIRROR DVCC V REF 500 CURRENT MIRROR AVCC GND ...

Page 13

AD6600 TIMING DIAGRAMS t ENCH ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 1_DRL D [10:0] RSSI [2:0] AB_OUT t ENCH ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 2 D [10:0] RSSI ...

Page 14

AD6600 t ENCH ENCODE ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 2 t H_DEN D [10:0] RSSI [2:0] t H_AEN AB_OUT CLK2 D [10:0] RSSI [2:0] AB_OUT 20 ENCODE 40 CLK2 ENCODE 8 CLK2 t ...

Page 15

AIN ATTEN AIN DETECT SET PEAK RSSI BIN ATTEN BIN 0dB, –12dB, –24dB A_SEL B_SEL THEORY OF OPERATION The AD6600, dual-channel, gain-ranging ADC integrates ana- log IF circuitry with high speed data conversion. Each analog input stage ...

Page 16

AD6600 Table I. Attenuator and Gain Settings Attenuator Gain Amp Total 0 dB + +12 dB +12 dB – – –24 dB +18 dB –6 ...

Page 17

Table II. Selecting AD6600 Operating Mode Output vs. Encode Clock Mode A_SEL B_SEL n Dual: A Single Single Not Valid 0 0 – A_SEL and B_SEL are not logic ...

Page 18

AD6600 If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown in Figure 19. VT 0.1 F ENCODE ECL/ PECL 0.1 F ENCODE VT Driving the ...

Page 19

AVCC 315 315 FROM GAIN STAGE ENCODE GND × × Figure 24 shows why settling is important for this circuit. If the 4×/8× amp does not settle (come out of clamp), the amplitude presented to the ADC will be decreased. ...

Page 20

... The resonant LC filter components (SEL2, C2 and C3) are omitted. The user must install proper values based on the IF chosen. See Understanding the External Analog Filter section of the data sheet for guidelines on selecting these components. Table VI. AD6600ST/PCB Bill of Material Description SMA Connector Ceramic Chip Capacitor 1206, 0.1 µF Tantalum Chip Capacitor, 10 µ ...

Page 21

BIN D0 D1 GND D2 AVCC D3 GND D4 AVCC D5 FLT FLT D6 D7 AVCC D8 AVCC D9 GND D10 AIN (MSB) AD6600 GND VCC GND VCC VCC VCC GND ...

Page 22

AD6600 ...

Page 23

Connecting the AD6600 with the AD6620 The AD6600 interfaces directly to the AD6620 Digital Receive Signal Processor as shown in Figure 31. No additional external components are required. Note that the layout requirements dis- cussed previously do apply and deviations ...

Page 24

AD6600 44-Terminal LQFP (Low-Profile Quad Plastic Flatpack) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). (ST-44) 0.063 (1.60) MAX 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN 0.006 (0.15) 0.002 (0.05) ...

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