AD9430-LVDS/PCB Analog Devices Inc, AD9430-LVDS/PCB Datasheet
AD9430-LVDS/PCB
Specifications of AD9430-LVDS/PCB
Related parts for AD9430-LVDS/PCB
AD9430-LVDS/PCB Summary of contents
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... CMOS mode, and a data clock output is available for proper output data timing. In LVDS mode, the chip provides data at the ENCODE clock rate. Fabricated on an advanced BiCMOS process, the AD9430 is available in a 100-lead, surface-mount plastic package (100 e-PAD TQFP) specified over the industrial temperature range (– ...
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... AD9430 TABLE OF CONTENTS DC Specifications ............................................................................. 4 AC Specifications.............................................................................. 6 Digital Specifications........................................................................ 7 Switching Specifications .................................................................. 8 Timing Diagrams.............................................................................. 9 Absolute Maximum Ratings.......................................................... 10 Explanation of Test Levels ......................................................... 10 ESD Caution................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Equivalent Circuits ......................................................................... 15 Typical Performance Characteristics ........................................... 16 Terminology .................................................................................... 23 Application Notes ........................................................................... 25 Theory of Operation .................................................................. 25 Encode Input............................................................................... 25 Analog Input ............................................................................... 26 DS Inputs (DS+, DS–)................................................................ 26 CMOS Outputs ...
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... Changes to Figure 68 (Evaluation Board—LVDS Mode) ......... 36 Updated Outline Dimensions ...................................................... 40 7/03—Rev Rev. B Changed order of Figure 1 and Figure 2 ...................................... 5 Updated TPC 13 .............................................................................14 Changes to LVDS OUTPUTS section..........................................20 Add New AD9430 EVALUATION BOARD, LVDS MODE Section ......................................................................................... 27 Updated OUTLINE DIMENSIONS ........................................... 32 3/03—Rev Rev. A Upgraded for AD9430-210 .............................................. Universal Changes to FEATURES ................................................................. 1 Changes to PRODUCT HIGHLIGHTS ...
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... V 5 Full IV 3.1 3.3 Full IV 3.0 3.3 Full VI 335 Full VI 55 Full VI 1.29 25°C V –7.5 Rev Page AD9430-210 Max Min Typ Max Guaranteed +3 – – –1 ± 0.3 +1 +1.5 –1 ± 0.3 +1.5 +1.5 –1.75 ± 0.3 +1.75 +2.25 –2.5 ± ...
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... Power consumption is measured with a dc input at rated ENCODE rate in LVDS output mode. DRVDD . Power consumption is measured with a dc input at rated ENCODE rate in CMOS output mode. DRVDD Rev Page AD9430-210 Max Min Typ Max 3.6 3.2 3.3 3.6 3.6 3.0 3.3 3.6 372 390 450 1.3 –7.5 AD9430 Unit mV/V ...
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... I 100 MHz 25°C V 240 MHz 25° MHz 25° MHz 25°C I 100 MHz 25°C V 240 MHz 25°C V 25°C V 25°C V Rev Page AD9430-170 AD9430-210 Typ Max Min Typ Max 65 62.5 64.5 65 62.5 64 62.5 64.5 65 62.5 64 10.6 10 ...
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... 2 DRVDD –0. 247 VI 1.125 Twos complement or binary Equivalent Circuits section pF 3.74 kΩ (1% tolerance). SET Rev Page AD9430 AD9430-210 Max Min Typ Max 0.2 1.575 1.375 1.5 1.575 6.5 3.2 5.5 6.5 4 2.0 0.8 0.8 190 190 DRVDD –0.05 0.05 0.05 ...
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... IV 15, 14 Full VI 2.0 Full VI 3.2 25°C V 0.5 25°C V 0.5 Full VI 1.8 2.7 Full IV 0.2 0.5 Full IV 14 25°C V 1.2 25°C V 0.25 25°C V Rev Page AD9430-210 Max Min Typ Max Unit 210 MSPS 40 40 MSPS 12.5 2 12.5 ns 12.5 2 12.5 ns –0 3.8 ...
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... CLK– DATA OUT DCO+ DCO– t CPD t SDS 14 CYCLES INVALID INVALID INVALID INVALID INVALID INVALID INVALID Figure 2. CMOS Timing Diagram N+1 1 N–13 N N–14 14 CYCLES Figure 3. LVDS Timing Diagram Rev Page N+2 N+1 N+3 N N+2 N+1 N+3 t CPD N+1 AD9430 ...
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... AD9430 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating AVDD, DRVDD 4 V Analog Inputs −0 AVDD + 0.5 V Digital Inputs −0 DRVDD + 0.5 V REFIN Inputs –0 AVDD + 0.5 V Digital Output Current 20 mA Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150° ...
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... NOTES 1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG ...
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... AD9430 Pin Number 47, 54, 62, 75, 83 48, 53, 61, 67, 74 AGND and DRGND should be tied together to a common ground plane Complement (DS−); can be tied to AVDD (as recommended) or left floating with no ill effects. Mnemonic Description CLK+ Clock Input—True. CLK– Clock Input—Complement. DB0 B Port Output Data Bit (LSB) ...
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... NOTES 1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG ...
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... AD9430 Pin Number 47, 54, 62, 75, 83 48, 53, 61, 67, 74 AGND and DRGND should be tied together to a common ground plane. 2 Pin 33 can be tied to AVDD (as recommended) or left floating with no ill effects Mnemonic Description VIN– Analog Input—Complement. GND Data Sync (Input)—Not Used in LVDS Mode. Tie to GND. ...
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... VIN– 20k Ω VDD Rev Page FULL K SCALE —> 1. —> 0.62 0.1 μ F VREF – 200 Ω SENSE 1k Ω DISABLE A1 VDD Figure 9. VREF, SENSE I/O DRVDD DX Figure 10. Data Outputs (CMOS Mode) DRVDD V V DX– DX Figure 11. Data Outputs (LVDS Mode) AD9430 ...
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... AD9430 TYPICAL PERFORMANCE CHARACTERISTICS Charts at 170 MSPS, 210 MSPS for –170, –210 grades, respectively. AVDD, DRVDD = 3 25°C, A scale = 1.536 V, internal reference unless otherwise noted. 0 SNR = 65.2dB –10 SINAD = 65.1dB H2 = –88.8dBc – –88.1dBc SFDR = 87dBc –30 –40 –50 –60 –70 –80 – ...
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... A (MHz) IN Frequency 210 MSPS –0.5 dBFS, LVDS Mode, Full Scale = 0. THIRD SECOND SFDR 0 50 100 150 200 250 300 A (MHz Figure 23. Harmonic Distortion (2 and 3 ) and SFDR vs. A Frequency 170 MSPS, CMOS Mode IN s AD9430 90 105 350 400 350 400 ...
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... AD9430 –170 SNR –170 SINAD 100 150 200 250 A (MHz) IN Figure 24. SNR and SINAD vs. A Frequency –0.5 dBFS, LVDS Mode SFDR 70 65 SNR 100 150 200 250 A (MHz) IN Figure 25. SNR and SINAD, SFDR vs 210 MSPS –0.5 dBFS, CMOS Mode SFDR = 75dBc – ...
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... ENCODE POSITIVE DUTY CYCLE (%) (A = 10.3 MHz @ –0.5 dBFS, 210 MSPS, LVDS Ω TYP (mA) LOAD Figure 34. V vs. I REFOUT LOAD % GAIN ERROR USING EXT REF –30 – TEMPERATURE (°C) Figure 35. Full-Scale Gain Error vs. Temperature = 10.3 MHz @ –0.5 dBFS, 170 MSPS/210 MSPS, LVDS) IN AD9430 ...
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... AD9430 1.250 1.245 1.240 1.235 1.230 1.225 2.5 2.7 2.9 3.1 3.3 AVDD (V) Figure 36. V Output Voltage vs. AVDD REF 95 THIRD 90 SECOND 85 SFDR –50 –30 – TEMPERATURE (°C) Figure 37. SNR, SINAD, and SFDR vs. Temperature (A = 10.3 MHz @ –0.5 dBFS, 170 MSPS AVDD = 3.135 ...
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... FULL-SCALE RANGE (V) Figure 46. SNR, SINAD, and SFDR vs. Full-Scale Range Full-Scale Range Varied by Adjusting VREF, 170 MSPS TPD TCPD –40 – TEMPERATURE (°C) Figure 47. Propagation Delay vs. Temperature, LVDS Mode, 170 MSPS/210 MSPS AD9430 47.6 SFDR 2.0 2.5 80 100 ...
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... AD9430 4.5 TCPD (CLOCKOUT RISING) 4.0 3.5 TPDR (DATA RISING) 3.0 2.5 –40 – TEMPERATURE (°C) Figure 48. Propagation Delay vs. Temperature, CMOS Mode, 170 MSPS/210 MSPS 900 800 700 600 500 TPDF (DATA FALLING) 400 300 200 100 60 80 100 Rev Page ...
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... FS is the full scale of the device for the frequency in question. SNR is the value of the particular input level. Signal is the signal level within the ADC, reported in dB below full scale. This value includes input levels both thermal and quantization noise. Rev Page AD9430 ⎛ ⎞ ⎜ ⎟ ⎜ ...
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... AD9430 Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc ...
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... A/D output. For that reason, considerable care has been taken in the design of the clock inputs of the AD9430, and the user is advised to give careful thought to the clock source. The AD9430 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLK+ and optimizes timing internally ...
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... Driving the DS inputs of each ADC by the same sync signal accomplishes this. An easy way to accomplish synchronization one-time sync at power-on reset. Note that when running the AD9430 in LVDS mode, set DS+ to ground and DS– the DS inputs are relevant only in CMOS output mode, simplifying the design for some applications as well as affording superior SNR/SINAD performance at higher 2 ...
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... NPR is a test that is commonly used to characterize the return path of cable systems where the signals are typically QAM signals with a noise-like frequency spectrum. NPR performance of the AD9430 was characterized in the lab yielding an effective NPR = 56 analog input of 19 MHz. This agrees with a theoretical maximum NPR of 57.1 dB for an 11-bit ADC at 13 ...
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... AVDD; connecting E47 to E46 powers the buffer from VCLK/V_XTAL. VOLTAGE REFERENCE The AD9430 has an internal 1.23 V voltage reference. The ADC uses the internal reference as the default when jumpers E24 to E27 and E25 to E26 are left open. The full scale can be increased by placing optional Resistor R3 ...
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... C1 FREQ 84.65608MHz SINGLE- ENDED 50 SOURCE CH2 60 80 Rev Page INHI 25 OPHI R1 AIN+ 100nF 50 5pF R AD9430 AD8351 G 25 OPLO AIN– INLO VOCM 100nF 2.8V 25 100nF Figure 57. Using the AD8351 on the AD9430 PCB AD9430 DIGITAL OUT ...
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... MHz) and monitor latch and ADC for toggling. SIGNAL GENERATOR REFIN 10MHz REFOUT SIGNAL GENERATOR The AD9430 evaluation board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. 3.3V 3.3V – – ...
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... Resistor 0402 Resistor 0402 Resistor 0402 Resistor pack 220 Ω SO16RES Inductor 0603 Transformer CD542 Optional Macom SM-22 Transformer AD9430BSV (−210) TQFP100 MC100LVEL16D SO8NB VCX86 SO14NB LVT574 SO20 JN00158 AD8351 Rev Page AD9430 Value Comments 0.1 μF C11, C18, C30, C33, ...
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... AD9430 PTMICA04 PTMICA04 PTMICA04 P4 P21 P22 GND 82 DRVDD GND 86 GND 87 VCC 88 VCC 89 VCC 90 GND 91 GND 92 GND 93 VCC 94 VCC 95 GND 96 GND 97 VCC 98 VCC 99 GND 100 Figure 59. Evaluation Board Schematic—CMOS Rev Page GND 48 VDD GND 41 VCC 40 VCC 39 GND 38 37 –ENC 36 GND 35 VCC ...
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... COMM AD8351 GND U9 R12 R25 25Ω 1.2kΩ ETC1-1-13 ETC1-1- GND GND PR SEC PR SEC AD9430 C32 C35 0.1μF 0.1μF C83 C84 0.01μF VAMP + C49 C48 10μF 0.1μF GND GND C39 R46 0.1μF 25Ω AMPINB AMPIN R47 C40 25Ω ...
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... AD9430 Figure 61. PCB Top-Side Silkscreen Figure 62. PCB Top-Side Copper Figure 63. PCB Ground Layer Figure 64. PCB Split Power Plane Rev Page ...
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... Figure 65. PCB Bottom-Side Copper Figure 66. PCB Bottom-Side Silkscreen Rev Page AD9430 ...
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... Jumper E47. E47 to E45 powers the buffer from AVDD; E47 to E46 powers the buffer from VCLK/V_XTAL (not in Table 11). VOLTAGE REFERENCE The AD9430 has an internal 1.23 V voltage reference. The ADC uses the internal reference as the default when jumpers E24 to E27 and E25 to E26 are left open. The full scale can be increased by placing optional resistor R3 ...
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... RF transformer Mini-Circuits ADT1-1WT RF amp AD8351 Optional crystal JN00158 or oscillator VF561 AD9430 TQFP-100 MC100LVEL16 SO8NB Rev Page AD9430 Value Comment 0.1 μF C3, C18, C39, C40 not placed 0.1 μF C33, C34, C37, C38 not placed not placed 20 pF C12, C13 not placed 100 Ω ...
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... AD9430 GND 82 DRVDD GND GND 87 VCC 88 VCC 89 VCC 90 GND 91 GND 92 GND 93 VCC 94 VCC 95 GND 96 GND 97 VCC 98 VCC 99 GND 100 PTM1CRO4 PTM1CRO4 P21 P22 Figure 67. Evaluation Board Schematic—LVDS Rev Page GND 47 DRVDD GND 40 VCC 39 VCC 38 GND 37 ~ENC 36 35 GND 34 VCC 33 32 ...
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... VDL VREF + C66 C18 C58 10μF 0.1μF 0.1μF GND GND R50 1kΩ GND VDL C37 0.1μF GND R47 25Ω C39 R49 0.1μF 25Ω AMPINB C40 R48 GND 0.1μF 25Ω AMPIN AD9430 C35 0.1μF + C63 10μF ...
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... AD9430 F Figure 70. PCB Top-Side Silkscreen—LVDS Figure 71. PCB Top-Side Copper—LVDS Figure 72. PCB Ground Layer—LVDS Figure 73. PCB Split Power Plane—LVDS Rev Page ...
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... Figure 74. PCB Bottom-Side Copper—LVDS Figure 75. PCB Bottom-Side Silkscreen—LVDS Rev Page AD9430 ...
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... BSC ORDERING GUIDE 1 Model Temperature Range AD9430BSV-170 −40°C to +85°C AD9430BSVZ-170 −40°C to +85°C AD9430BSV-210 −40°C to +85°C AD9430BSVZ-210 −40°C to +85° RoHS Compliant Part. 14.00 BSC PIN 1 TOP VIEW (PINS DOWN ...
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... NOTES Rev Page AD9430 ...
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... AD9430 NOTES ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02607-0-9/10(E) Rev Page ...