AD9433/PCB Analog Devices Inc, AD9433/PCB Datasheet

BOARD EVAL FOR AD9433

AD9433/PCB

Manufacturer Part Number
AD9433/PCB
Description
BOARD EVAL FOR AD9433
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9433/PCB

Rohs Status
RoHS non-compliant
FEATURES
IF sampling up to 350 MHz
SNR: 67.5 dB, f
SFDR: 83 dBc, f
SFDR: 72 dBc, f
2 V p-p analog input range
On-chip clock duty cycle stabilization
On-chip reference and track-and-hold
SFDR optimization circuit
Excellent linearity
750 MHz full power analog bandwidth
Power dissipation: 1.35 W (typical) at 125 MSPS
Twos complement or offset binary data format
5.0 V analog supply operation
2.5 V to 3.3 V TTL/CMOS outputs
APPLICATIONS
Cellular infrastructure communication systems
Wideband carrier frequency systems
Communications test equipment
Radar and satellite ground systems
GENERAL INTRODUCTION
The AD9433 is a 12-bit, monolithic sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit and is
designed for ease of use. The product operates up to a 125 MSPS
conversion rate and is optimized for outstanding dynamic per-
formance in wideband and high IF carrier systems.
The ADC requires a 5 V analog power supply and a differential
encode clock for full performance operation. No external refer-
ence or driver components are required for many applications.
The digital outputs are TTL-/CMOS-compatible, and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
DNL: ±0.25 LSB (typical)
INL: ±0.5 LSB (typical)
3G single- and multicarrier receivers
IF sampling schemes
Point-to-point radios
LMDS, wireless broadband
MMDS base station units
Cable reverse path
IN
IN
IN
up to Nyquist at 105 MSPS
= 70 MHz at 105 MSPS
= 150 MHz at 105 MSPS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
A user-selectable, on-chip proprietary circuit optimizes
spurious-free dynamic range (SFDR) vs. signal-to-noise and
distortion (SINAD) ratio performance for different input signal
frequencies, providing as much as 83 dBc SFDR performance
over the dc to 70 MHz band.
The encode clock supports either differential or single-ended
input and is PECL-compatible. The output format is user-
selectable for offset binary or twos complement and provides
an overrange (OR) signal.
Fabricated on an advanced BiCMOS process, the AD9433 is
available in a 52-lead thin quad flat package (TQFP_EP) that
is specified over the industrial temperature range of −40°C to
+85°C. The AD9433 is pin-compatible with the AD9432.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
ENCODE
ENCODE
12-Bit, 105 MSPS/125 MSPS,
V
AIN
AIN
IF Sampling.
The AD9433 maintains outstanding ac performance up to
input frequencies of 350 MHz. Suitable for 3G wideband
cellular IF sampling receivers.
Pin-Compatibility with the AD9432.
The AD9433 has the same footprint and pin layout as the
AD9432 12-bit 80 MSPS/105 MSPS ADC.
SFDR Performance.
A user-selectable, on-chip circuit optimizes SFDR
performance as much as 83 dBc from dc to 70 MHz.
Sampling Rate.
At 125 MSPS, the AD9433 is ideally suited for wireless and
wired broadband applications such as LMDS/MMDS and
cable reverse path.
CC
FUNCTIONAL BLOCK DIAGRAM
ENCODE
TIMING
T/H
GND
©2001–2009 Analog Devices, Inc. All rights reserved.
VREFOUT
PIPELINE
Figure 1.
ADC
IF Sampling ADC
REF
VREFIN
12
STAGING
OUTPUT
AD9433
AD9433
www.analog.com
12
V
D11 TO D0
DFS
SFDR
MODE
DD

Related parts for AD9433/PCB

AD9433/PCB Summary of contents

Page 1

FEATURES IF sampling up to 350 MHz SNR: 67.5 dB Nyquist at 105 MSPS IN SFDR: 83 dBc MHz at 105 MSPS IN SFDR: 72 dBc 150 MHz at 105 MSPS IN ...

Page 2

AD9433 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Introduction ....................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 4 Switching Specifications ...

Page 3

SPECIFICATIONS DC SPECIFICATIONS internal reference; differential encode input, unless otherwise noted Table 1. Parameter Temp RESOLUTION ACCURACY No Missing Codes Full Offset Error Full 1 Gain Error 25°C 2 Differential ...

Page 4

AD9433 Parameter Temp DIGITAL OUTPUTS Logic 1 Voltage Full Logic 0 Voltage Full Output Coding 1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and p-p ...

Page 5

SWITCHING SPECIFICATIONS differential encode input, unless otherwise noted Table 3. Parameter Encode Rate Encode Pulse Width High ( Encode Pulse Width Low ( Aperture Delay (t ...

Page 6

AD9433 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Analog Inputs Digital Inputs Digital Output Current Operating Temperature Range ( Storage Temperature Range Maximum Junction Temperature ( Stresses above those listed under Absolute Maximum ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin No. Mnemonic 11, 33, GND 34, 35, 38, 39, 40, 43, 48 10, 36, 37 44, 47 ...

Page 8

AD9433 TYPICAL PERFORMANCE CHARACTERISTICS 0 SNR = 67.5dB –10 SFDR = 85dBFS –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 13.1 26.3 FREQUENCY (MHz) Figure 4. FFT 105 MSPS 49.3 MHz, Differential ...

Page 9

IMD3 = 92dBFS –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 7.5 15.0 22.5 30.0 FREQUENCY (MHz) Figure 10. FFT 105 MSPS 49.3 MHz and 50.3 MHz Differential ...

Page 10

AD9433 –95 WORST OTHER (dBc) –90 THIRD HARMONIC (dBc) –85 –80 SECOND HARMONIC (dBc) –75 SNR (dB) –70 – DUTY CYCLE HIGH (%) Figure 16. Dynamic Performance vs. Encode Duty Cycle ...

Page 11

SNR = 66.8dB –10 SFDR = 83dBFS –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 7.5 15.0 22.5 30.0 FREQUENCY (MHz) Figure 22. FFT 105 MSPS 70.3 MHz, Differential AIN @ ...

Page 12

AD9433 0 SNR = 64dB –10 SFDR = 78dBFS –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 7.5 15.0 22.5 30.0 FREQUENCY (MHz) Figure 28. FFT 105 MSPS 150.3 MHz, Differential AIN ...

Page 13

FREQUENCY (MHz) Figure 34. FFT 76.8 MSPS 59.6 MHz, Two WCDMA Carriers Differential AIN, SFDR Mode Enabled 0 ...

Page 14

AD9433 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge ...

Page 15

Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be a harmonic. May be reported in dBc (degrades as ...

Page 16

AD9433 EQUIVALENT CIRCUITS V CC VREFIN Figure 36. Voltage Reference Input Circuit V CC 3.75kΩ 3.75kΩ AIN AIN 15kΩ 15kΩ Figure 37. Analog Input Circuit Figure 38. Digital Output Circuit V Figure 39. Voltage Reference Output Circuit ...

Page 17

THEORY OF OPERATION The AD9433 is a 12-bit pipeline converter that uses a switched- capacitor architecture. Optimized for high speed, this converter provides flat dynamic performance up to and beyond the Nyquist limit. DNL transitional errors are calibrated at final ...

Page 18

AD9433 ANALOG INPUT The analog input to the AD9433 is a differential buffer. The input buffer is self-biased by an on-chip resistor divider that sets the dc common-mode voltage to a nominal 4 V (see the Equivalent Circuits section). Rated ...

Page 19

APPLICATIONS INFORMATION LAYOUT INFORMATION A multilayer board is recommended to achieve best results highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the ...

Page 20

AD9433 OUTLINE DIMENSIONS 1.20 0.75 MAX 0.60 0.45 SEATING PLANE 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 3.5° 0.15 0° 0.05 0.08 MAX COPLANARITY VIEW A ROTATED 90 ° CCW ORDERING GUIDE Model Temperature Range 1 AD9433BSVZ-105 −40°C to ...

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