AD9748ACP-PCB Analog Devices Inc, AD9748ACP-PCB Datasheet

no-image

AD9748ACP-PCB

Manufacturer Part Number
AD9748ACP-PCB
Description
BOARD EVAL FOR AD9748ACP
Manufacturer
Analog Devices Inc
Series
TxDAC®r
Datasheet

Specifications of AD9748ACP-PCB

Rohs Status
RoHS non-compliant
Number Of Dac's
1
Number Of Bits
8
Outputs And Type
1, Differential
Sampling Rate (per Second)
210M
Data Interface
Parallel
Settling Time
11ns
Dac Type
Current
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9748
FEATURES
High performance member of pin-compatible
Linearity
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.20 V reference
CMOS-compatible digital interface
32-lead LFCSP
Edge-triggered latches
Fast settling: 11 ns to 0.1% full-scale
GENERAL DESCRIPTION
The AD9748
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC
family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit
DACs, is specifically optimized for the transmit signal path of
communication systems. All of the devices share the same
interface options, small outline package, and pinout, providing
an upward or downward component selection path based on
performance, resolution, and cost. The AD9748 offers
exceptional ac and dc performance while supporting update
rates up to 210 MSPS.
The AD9748’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to 60 mW with a slight degradation in
performance by lowering the full-scale current output. In
addition, a power-down mode reduces the standby power
dissipation to approximately 15 mW. A segmented current
source architecture is combined with a proprietary switching
technique to reduce spurious components and enhance
dynamic performance.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
TxDAC product family
0.1 LSB DNL
0.1 LSB INL
1
is an 8-bit resolution, wideband, third generation
8-Bit, 210 MSPS TxDAC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
APPLICATIONS
Communications
Direct digital synthesis (DSS)
Instrumentation
R
Edge-triggered input latches and a 1.2 V temperature-
compensated band gap reference have been integrated to
provide a complete monolithic DAC solution. The digital inputs
support 3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
1
SET
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
CLK+
CLK–
32-lead LFCSP.
The AD9748 is the 8-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
Differential or single-ended clock input (LVPECL or
CMOS), supports 210 MSPS conversion rate.
Data input supports twos complement or straight binary
data coding.
Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
On-chip voltage reference: The AD9748 includes a 1.2 V
temperature-compensated band gap voltage reference.
0.1μF
3.3V
3.3V
FUNCTIONAL BLOCK DIAGRAM
REFIO
FS ADJ
DVDD
DCOM
CLKVDD
CLKCOM
SLEEP
1.2V REF
DIGITAL DATA INPUTS (DB7–DB0)
© 2005 Analog Devices, Inc. All rights reserved.
SEGMENTED
SWITCHES
Figure 1.
®
150pF
LATCHES
D/A Converter
CURRENT
SOURCE
SWITCHES
ARRAY
LSB
3.3V
AVDD
AD9748
AD9748
www.analog.com
ACOM
IOUTA
IOUTB
MODE
CMODE

Related parts for AD9748ACP-PCB

AD9748ACP-PCB Summary of contents

Page 1

FEATURES High performance member of pin-compatible TxDAC product family Linearity 0.1 LSB DNL 0.1 LSB INL Twos complement or straight binary data format Differential current outputs Power dissipation: 135 mW @ 3.3 V Power-down mode: ...

Page 2

AD9748 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Dynamic Specifications ............................................................... 4 Digital Specifications ................................................................... 5 ...

Page 3

SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error ...

Page 4

AD9748 DYNAMIC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) CLOCK 1 Output ...

Page 5

DIGITAL SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance ...

Page 6

AD9748 ABSOLUTE MAXIMUM RATINGS Table 4. With Respect to Parameter Min AVDD ACOM −0.3 DVDD DCOM −0.3 CLKVDD CLKCOM −0.3 ACOM DCOM −0.3 ACOM CLKCOM −0.3 DCOM CLKCOM −0.3 AVDD DVDD −3.9 AVDD CLKVDD −3.9 DVDD CLKVDD −3.9 CLK+, CLK−, ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 27 DB7 (MSB) Most Significant Data Bit (MSB 32, 1 DB6 to DB1 Data Bits DB0 (LSB) Least Significant Data ...

Page 8

AD9748 TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS 55 5mA 50 10mA 2.5mA 20mA (MHz) OUT Figure 5. SINAD vs 100 MSPS (Single-Ended Output) OUTFS 55 10mA 50 5mA ...

Page 10

AD9748 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY (MHz) Figure 11. Single-Tone Spectral Plot @ 125 MSPS (Single-Ended Output 165MSPS CLOCK – 49MHz OUT SFDR = ...

Page 11

FUNCTIONAL DESCRIPTION Figure 15 shows a simplified block diagram of the AD9748. The AD9748 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing ...

Page 12

AD9748 The control amplifier allows a wide (10:1) adjustment span of I over range by setting I OUTFS μA and 625 μA. The wide adjustment span of I several benefits. The first relates directly ...

Page 13

The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ in parallel with 5 pF also slightly dependent on the ...

Page 14

AD9748 DAC TIMING Input Clock and Data Timing Relationship Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the time at which the input data changes. The AD9748 is rising edge ...

Page 15

APPLYING THE AD9748 Output Configurations The following sections illustrate some typical output configurations for the AD9748. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications OUTFS requiring the optimum dynamic performance, a ...

Page 16

AD9748 DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to-single- ended conversion, as shown in Figure 26. The AD9748 is configured with two equal load resistors, R differential voltage developed across IOUTA ...

Page 17

POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the printed circuit board is as important as the circuit ...

Page 18

AD9748 EVALUATION BOARD GENERAL DESCRIPTION The AD9748 evaluation boards allow for easy setup and testing of the product in the LFCSP package. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to evaluate the ...

Page 19

L1 BEAD TB1 1 BLK C2 C3 10μF 0.1μF TP2 6.3V TB1 2 L2 BEAD TB3 1 BLK C7 C4 0.1μF 10μF TP4 6.3V TB3 2 L3 BEAD TB4 1 BLK C9 C5 0.1μF 10μF TP6 6.3V TB4 2 R3 ...

Page 20

AD9748 32 1 DB7 DB8 DB7 2 31 DB6 DB9 DB6 30 3 DVDD DB10 DVDD 4 29 DB5 DB11 DB5 5 28 DB4 DB12 DB4 27 6 DB3 DB13 DB3 7 26 DB2 DCOM1 DB2 25 8 DB1 SLEEP ...

Page 21

Figure 35. Evaluation Board Layout—Primary Side Figure 36. Evaluation Board Layout—Secondary Side Rev Page AD9748 ...

Page 22

AD9748 Figure 37. Evaluation Board Layout—Ground Plane Figure 38. Evaluation Board Layout—Power Plane Rev Page ...

Page 23

Figure 39. Evaluation Board Layout Assembly—Primary Side Figure 40. Evaluation Board Layout Assembly—Secondary Side Rev Page AD9748 ...

Page 24

... AD9748ACPRL7 −40°C to +85°C 1 AD9748ACPZ −40°C to +85°C 1 AD9748ACPZRL7 −40°C to +85°C AD9748ACP-PCB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03211–0–12/05(A) 5.00 BSC SQ ...

Related keywords