EVAL-AD7476ACB Analog Devices Inc, EVAL-AD7476ACB Datasheet - Page 18

• Manufacturer Part Number: EVAL-AD7476ACB
• Description: BOARD EVAL FOR AD7476A
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7476ACB

• Rohs Status: RoHS non-compliant
• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 17.5mW @ 1MSPS, 5 V
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7476A
• Lead Free Status / Rohs Status: Not Compliant

AD7476A/AD7477A/AD7478A
MODES OF OPERATION
The modes of operation for the AD7476A/AD7477A/AD7478A
are selected by controlling the (logic) state of the CS signal during
a conversion. There are two possible modes of operation: normal
and power-down. The point at which CS is pulled high after the
conversion has been initiated determines whether the AD7476A/
AD7477A/AD7478A enters power-down mode. Similarly, if
already in power-down, CS can control whether the device returns
to normal operation or remains in power-down. These modes of
operation are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for different application
requirements.
NORMAL MODE
This mode is intended for the fastest throughput rate performance.
In normal mode, the user does not have to worry about any
power-up times because AD7476A/AD7477A/AD7478A
remain fully powered at all times. Figure 20 shows the general
diagram of the operation of the AD7476A/AD7477A/AD7478A
in this mode. The conversion is initiated on the falling edge of
CS as described in the
the part remains fully powered up at all times,
low until at least 10 SCLK falling edges have elapsed after the
falling edge of CS . If CS is brought high any time after the 10th
SCLK falling edge but before the end of the t
remains powered up, but the conversion is terminated and
SDATA goes back into three-state. For the AD7476A, 16 serial
clock cycles are required to complete the conversion and access
the complete conversion results. For the AD7477A and AD7478A,
a minimum of 14 and 12 serial clock cycles are required to com-
plete the conversion and access the complete conversion results,
respectively. CS can idle high until the next conversion or idle
low until CS returns high sometime prior to the next conversion
(effectively idling CS low). Once a data transfer is complete
(SDATA has returned to three-state), another conversion can be
initiated after the quiet time, t
low again.
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions is performed
at a high throughput rate and the ADC is then powered down
for a relatively long duration between these bursts of several
conversions. When the AD7476A/AD7477A/AD7478A are in
power-down, all analog circuitry is powered down. To enter
power-down, the conversion process must be interrupted by
bringing CS high anywhere after the second falling edge of SCLK
and before the 10th falling edge of SCLK, as shown in
Serial Interface
QUIET
, has elapsed by bringing CS
section. To ensure that
CONVERT
CS must remain
, the part
Figure 22
Rev. E | Page 18 of 28
.
Once
part enters power-down, the conversion that was initiated by
the falling edge of CS is terminated, and SDATA goes back into
three-state. If CS is brought high before the second SCLK falling
edge, the part remains in normal mode and does not power
down. This avoids accidental power-down due to glitches on the
CS line. In order to exit this mode of operation and power up
the AD7476A/AD7477A/AD7478A again, a dummy conversion
is performed. On the falling edge of CS , the device begins to
power up and continues to power up as long as CS is held low
until after the falling edge of the 10th SCLK. The device is fully
powered up once 16 SCLKs have elapsed, and valid data results
from the next conversion, as shown in
brought high before the 10th falling edge of SCLK, then the
AD7476A/AD7477A/AD7478A go back into power-down. This
avoids accidental power-up due to glitches on the CS line or an
inadvertent burst of eight SCLK cycles while CS is low.
Although the device can begin to power up on the falling edge
of CS , it powers down again on the rising edge of CS as long as it
occurs before the 10th SCLK falling edge.
POWER-UP TIME
The power-up time of the AD7476A/AD7477A/AD7478A is
1 μs, meaning that with any frequency of SCLK up to 20 MHz,
one dummy cycle is always sufficient to allow the device to
power up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, t
goes back into three-state after the dummy conversion to the
next falling edge of CS . When running at a 1 MSPS throughput
rate, the AD7476A/AD7477A/AD7478A power up and acquire
a signal within 0.5 LSB in one dummy cycle, that is, 1 μs.
When powering up from the power-down mode with a dummy
cycle, as in Figure 22, the track-and-hold that was in hold mode
while the part was powered down returns to track mode after
the first SCLK edge the part receives after the falling edge of CS .
This is shown as Point A in
frequency, one dummy cycle is sufficient to power up the device
and acquire V
cycle of 16 SCLKs must always elapse to power up the device
and acquire V
and acquire the input signal. If, for example, a 5 MHz SCLK
frequency is applied to the ADC, the cycle time becomes 3.2 μs.
In one dummy cycle, 3.2 μs, the part powers up and V
acquires fully. However, after 1 μs with a 5 MHz SCLK, only five
SCLK cycles would have elapsed. At this stage, the ADC would
fully power up and acquire the signal. In this case, the
brought high after the 10th SCLK falling edge and brought low
again after a time, t
CS has been brought high in this window of SCLKs, the
QUIET
, must still be allowed from the point where the bus
IN
IN
, it does not necessarily mean that a full dummy
fully; 1 μs is sufficient to power up the device
QUIET
, to initiate the conversion.
Figure 22
. Although at any SCLK
Figure 24
. If
CS is
IN
CS can be