BOARD EVAL FOR AD9956

AD9956/PCB

Manufacturer Part NumberAD9956/PCB
DescriptionBOARD EVAL FOR AD9956
ManufacturerAnalog Devices Inc
AD9956/PCB datasheet
 


Specifications of AD9956/PCB

Module/board TypeEvaluation BoardFor Use With/related ProductsAD9956
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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FEATURES
400 MSPS internal DDS clock speed
48-bit frequency tuning word
14-bit programmable phase offset
Integrated 14-bit DAC
Excellent dynamic performance
Phase noise ≤ 135 dBc/Hz @ 1 KHz offset
−80 dB SFDR @ 160 MHz (±100 KHz offset I
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 phase/frequency profiles
1.8 V supply for device operation
DELTA
FREQUENCY
TUNING WORD
FREQUENCY
ACCUMULATOR
DELTA
FREQUENCY
RAMP RATE
24
PLL_LOCK/SYNC_IN
I/O_UPDATE
SYNC_CLK
SYNC_OUT
RF-DIVIDER
÷R
REFCLK
REFCLK
CML CLOCK DRIVER
DRV DRV DRV_RSET
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
2.7 GHz DDS-Based AgileRF
3.3 V supply for I/O and charge pump
Software controlled power-down
48-lead LFCSP package
Automatic linear frequency sweeping capability (in DDS)
Programmable charge pump current (up to 4 mA)
Phase modulation capability
Multichip synchronization
Dual-mode PLL lock detect
)
OUT
655 MHz CML-mode PECL-compliant driver
APPLICATIONS
Agile LO frequency synthesis
FM chirp source for radar and scanning systems
Automotive radars
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
DDS CORE
PHASE
48
OFFSET
19
PHASE
ACCUMULATOR
FTW
PHASE
48
OFFSET
14
WORD
SYSCLK
16
TIMING AND CONTROL LOGIC
OSCILLATOR
SYSCLK
÷4
3
FROM PLLOSC
PS<2:0> RESET I/O PORT
PLLREF/
PLLREF
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
TM
Synthesizer
AD9956
DAC_RSET
PHASE TO
14
AMPLITUDE
DAC
CONVERSION
SYSCLK
LOCK
CHARGE
DETECT
PUMP
SCALER
÷M
3
Φ
BUFFER
CHARGE
PUMP
÷N
BUFFER
CP_RSET
PLLOSC/
PLLOSC
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
IOUT
IOUT
I/O_RESET
CP_OUT

AD9956/PCB Summary of contents

  • Page 1

    FEATURES 400 MSPS internal DDS clock speed 48-bit frequency tuning word 14-bit programmable phase offset Integrated 14-bit DAC Excellent dynamic performance Phase noise ≤ 135 dBc/ KHz offset −80 dB SFDR @ 160 MHz (±100 KHz offset I ...

  • Page 2

    AD9956 TABLE OF CONTENTS Product Overview............................................................................. 3 Specifications..................................................................................... 4 Loop Measurement Conditions.................................................. 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 13 Typical Application Circuits.......................................................... 16 Application Circuit Explanations............................................. 17 General ...

  • Page 3

    PRODUCT OVERVIEW The AD9956 is Analog Devices’ newest AgileRF synthesizer. The device is comprised of DDS and PLL circuitry. The DDS features a 14-bit DAC operating 400 MSPS and a 48-bit frequency tuning word (FTW). The PLL ...

  • Page 4

    AD9956 SPECIFICATIONS AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± DRV_R = 4.02 kΩ, unless otherwise noted. SET Table 1. Parameter RF DIVIDER (REFCLK ) INPUT SECTION (÷R) RF Divider ...

  • Page 5

    Parameter LOGIC INPUTS (SDI/O, I/O_RESET, RESET, I/O_UPDATE, PS0 to PS2, SYNC_IN Input High Voltage Input Low Voltage Input Current INH INL C , Maximum Input Capacitance IN LOGIC OUTPUTS (SDO, SYNC_OUT, ...

  • Page 6

    AD9956 Parameter 160 MHz Analog Out (±1 MHz) 160 MHz Analog Out (±250 kHz) 160 MHz Analog Out (±50 kHz) DAC Residual Phase Noise 19.7 MHz F OUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset ...

  • Page 7

    Parameter 7 Latencies/Pipeline Delays I/O Update to DAC Frequency Change I/O Update to DAC Phase Change PS<2:0> to DAC Frequency Change PS<2:0> to DAC Phase Change I/O Update to CP_OUT Scaler Change I/O Update to Frequency Accumulator Step Size Change ...

  • Page 8

    AD9956 Parameter TOTAL SYSTEM JITTER AND PHASE NOISE FOR 105.33 MHz ADC CLOCK GENERATION CIRCUIT Converter Limiting Jitter Resultant SNR Phase Noise of Fundamental @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset ...

  • Page 9

    LOOP MEASUREMENT CONDITIONS 622 MHz OC-12 Clock VCO = Sirenza 190-640T Reference = Wenzel 500-10116 (30.3 MHz) Loop Filter = 10 kHz BW, 60° Phase Margin C1 = 170 nF 14.4 Ω 5.11 µ ...

  • Page 10

    AD9956 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Analog Supply Voltage (AVDD Digital Supply Voltage (DVDD Digital I/O Supply Voltage 3.6 V (DVDD_I/0) 3.6 V Charge Pump Supply Voltage (CPVDD) Maximum Digital Input Voltage −0.5 V ...

  • Page 11

    PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. For the device to function properly, the paddle MUST be attached to analog ground. AGND ...

  • Page 12

    AD9956 Table 3. 48-Lead LFCSP Pin Function Description Pin No. Mnemonic 26, 30, AGND 34, 37, 43 27, 38, AVDD 44 IOUT 6 IOUT 9 I/O_RESET 10 RESET 11, 25 DVDD ...

  • Page 13

    TYPICAL PERFORMANCE CHARACTERISTICS DELTA 1 [T1] RBW 500Hz REF LVL –84.82dB VBW 500Hz 0dBm –404.80961924kHz SWT 0 1 –10 –20 –30 –40 –50 –60 –70 –80 1 –90 –100 CENTER 10.1MHz 100kHz/ Figure 4. AD9956 DAC Performance: 400 MSPS Clock, ...

  • Page 14

    AD9956 DELTA 1 [T1] RBW 500kHz –78.13dB VBW 500kHz REF LVL –100.20040080kHz SWT 0dBm 0 1 –10 –20 –30 –40 –50 –60 –70 –80 1 –90 –100 CENTER 159.5MHz 100kHz/ Figure 10. AD9956 DAC Performance: 400 MSPS Clock, 160 MHz ...

  • Page 15

    FREQUENCY (Hz) Figure 16. RF Divider and CML Driver Residual Phase Noise (840 MHz In, 105 MHz ...

  • Page 16

    AD9956 TYPICAL APPLICATION CIRCUITS 25MHz DETECTOR/CHARGE PUMP CRYSTAL ÷M ÷N 25MHz CRYSTAL PHASE FREQUENCY PLLREF 400MHz CP_OUT VCO LPF PLLOSC DRIVER ÷R AD9956 DAC DDS Figure 22. Dual-Clock Configuration PLLREF CP_OUT LPF PLLOSC DAC DDS LPF AD9956 Figure 23. Fractional-Divider ...

  • Page 17

    EXTERNAL REFERENCE DDS APPLICATION CIRCUIT EXPLANATIONS Dual-Clock Configuration In this loop 16, and The DDS tuning word is also equal to ¼ so that the frequency of CLOCK 1’ equals the frequency ...

  • Page 18

    AD9956 GENERAL DESCRIPTION DDS CORE The DDS can create digital phase relationships by clocking a 48-bit accumulator. The incremental value loaded into the accumulator, known as the frequency tuning word, controls the overflow rate of the accumulator. Similar to a ...

  • Page 19

    CML DRIVER For clocking applications, an on-chip current mode logic (CML) driver is included. This CML driver generates very low jitter clock edges. The outputs of the CML driver are current outputs and drives PECL levels when terminated into a ...

  • Page 20

    AD9956 MODES OF OPERATION DDS MODES OF OPERATION Single-Tone Mode This is the default mode of operation for the DDS core. The phase accumulator runs at a fixed frequency, as per the active profile’s tuning word. Likewise, any phase offset ...

  • Page 21

    Automatic Synchronization In automatic synchronization mode, the device is placed into slave mode and automatically aligns the internal SYNC_CLK to a master SYNC_CLK signal, supplied on the SYNC_IN input. When this bit is enabled, the PLL_LOCK is not available as ...

  • Page 22

    AD9956 SERIAL PORT OPERATION An AD9956 serial data-port communication cycle has two phases. Phase 1 is the instruction cycle, which is the writing of an instruction byte to the AD9956, coincident with the first eight SCLK rising edges. The instruction ...

  • Page 23

    INSTRUCTION BYTE The instruction byte contains the following information: Table R/ R/Wb—Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte ...

  • Page 24

    AD9956 REGISTER MAP AND DESCRIPTION Table 5. Register Name (Serial Bit Address) Range (MSB) Bit 7 1 Control <31:24> Open Function Register 1 <23:16> LOAD SRR @ (CFR1) I/O_UPDATE (0x00) <15:8> LSB First <7:0> Digital Power- Down Control <39:32> DAC ...

  • Page 25

    Register Name (Serial Address) Bit Range Profile Control Register <63:56> No. 0 (PCR0) (0x06) <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Profile Control Register <63:56> No. 1 (PCR1) (0x07) <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Profile Control Register <63:56> ...

  • Page 26

    AD9956 Register Name Bit (MSB) (Serial Address) Range Bit 7 Profile Control <63:56> Register <55:48> No. 4 (PCR4) (0x0A) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Profile Control <63:56> Register <55:48> No. 5 (PCR5) (0x0B) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> ...

  • Page 27

    CONTROL FUNCTION REGISTER DESCRIPTIONS Control Function Register 1 (CFR1) This control register is comprised of four bytes, all of which must be written during a write operation involving CFR1. CFR1 is used to control various functions, features, and operating modes ...

  • Page 28

    AD9956 CFR1 <17> Linear Sweep Enable This bit turns on the frequency accumulator, which enables the DDS to perform linear sweeping. CFR1<17> (default). The DDS generates frequencies in single-tone mode. CFR1<17> The DDS uses the frequency ...

  • Page 29

    CFR1<3> (default). The automatic synchronization function of the DDS core is disabled. CFR1<3> The automatic synchronization function is on. The device is slaved to an external reference and adjusts the internal SYNC_CLK to match the external ...

  • Page 30

    AD9956 CFR2<28:26> Clock Driver Falling Edge Control These bits control the slew rate of the CML clock driver output’s falling edge. When these bits are on, additional current is sent to the output driver to increase the rising edge slew ...

  • Page 31

    CFR2<15:12> PLLREF Divider Control Bits (÷N) These 4 bits set the PLLREF divider (÷N) ratio where value equal 16. CFR2<15:12> = 0000 means that and CFR2<15:12> = 1111 means that N ...

  • Page 32

    ... ORDERING GUIDE Model Temperature Range 1 AD9956YCPZ –40°C to +125°C 1 AD9956YCPZ-REEL –40°C to +125°C AD9956/PCB AD9956-VCO/PCB Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 7.00 BSC SQ 0.60 MAX ...