AD9956/PCB Analog Devices Inc, AD9956/PCB Datasheet - Page 7

• Manufacturer Part Number: AD9956/PCB
• Description: BOARD EVAL FOR AD9956
• Manufacturer: Analog Devices Inc

Specifications of AD9956/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD9956
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Parameter
RF DIVIDER/CML DRIVER EQUIVALENT
INTRINSIC TIME JITTER
RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE
TOTAL SYSTEM TIME JITTER FOR 622 MHz CLOCK
Latencies/Pipeline Delays
F
F
F
F
F
F
12 kHz to 5 MHz Bandwidth
IN
IN
IN
IN
IN
IN
I/O Update to DAC Frequency Change
I/O Update to DAC Phase Change
PS<2:0> to DAC Frequency Change
PS<2:0> to DAC Phase Change
I/O Update to CP_OUT Scaler Change
I/O Update to Frequency Accumulator
I/O Update to Frequency Accumulator
BW = 12 kHz −> 400 kHz
BW = 12 kHz −> 1.3 MHz
BW = 12 kHz −> 5 MHz
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
> 1 MHz
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
>3 MHz
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
>3 MHz
= 414.72 MHz, F
= 1244.16 MHz, F
= 2488.32 MHz, F
= 157.6 MHz, F
= 1240 MHz, F
= 2488MHz, F
Step Size Change
Ramp Rate Change
OUT
OUT
OUT
OUT
= 622 MHz
OUT
OUT
= 155 MHz
= 19.7 MHz
= 51.84 MHz
= 155.52 MHz
= 622.08 MHz
7
Min
Rev. A | Page 7 of 32
Typ
33
33
29
29
4
4
136
101
108
−115
−126
−134
−143
−150
−151
−111
−122
−129
−138
−146
−150
−153
−97
−110
−120
−126
−136
−141
−144
0.7
4
Max
Unit
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
f
f
f
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps rms
S
S
S
rms
rms
rms
Test Conditions/Comments
OC1, RF Divider R = 8
OC3, RF Divider R = 8
OC12, RF Divider R = 4
RF Divider R = 8
RF Divider R = 8
RF Divider R = 4
See the Loop Measurement Condi-
tions section
AD9956