AD9956-VCO/PCB Analog Devices Inc, AD9956-VCO/PCB Datasheet
AD9956-VCO/PCB
Specifications of AD9956-VCO/PCB
Related parts for AD9956-VCO/PCB
AD9956-VCO/PCB Summary of contents
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... TIMING AND CONTROL LOGIC OSCILLATOR SYSCLK ÷4 3 FROM PLLOSC PS<2:0> RESET I/O PORT PLLREF/ PLLREF Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 TM Synthesizer AD9956 DAC_RSET PHASE TO 14 AMPLITUDE DAC CONVERSION SYSCLK LOCK CHARGE DETECT PUMP SCALER ÷M 3 Φ ...
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... AD9956 TABLE OF CONTENTS Product Overview............................................................................. 3 Specifications..................................................................................... 4 Loop Measurement Conditions.................................................. 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 13 Typical Application Circuits.......................................................... 16 Application Circuit Explanations............................................. 17 General Description ....................................................................... 18 DDS Core..................................................................................... 18 PLL Circuitry .............................................................................. 18 REVISION HISTORY 9/04—Data Sheet Changed from Rev Rev. A Changes to the Pin Configuration ...
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... VCO, enables the synthesis of digitally programmable, frequency-agile analog output sinusoidal wave- forms up to 2.7 GHz. The AD9956 is designed to provide fast frequency hopping and fine tuning resolution (48-bit frequency tuning word). Information is loaded into the AD9956 via a serial I/O port that has a device write-speed of 25 Mb/s ...
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... AD9956 SPECIFICATIONS AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± DRV_R = 4.02 kΩ, unless otherwise noted. SET Table 1. Parameter RF DIVIDER (REFCLK ) INPUT SECTION (÷R) RF Divider Input Range Input Capacitance (DC) Input Impedance (DC) Input Duty Cycle Input Power/Sensitivity Input Voltage Level PHASE FREQUENCY DETECTOR/CHARGE PUMP ...
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... AVDD − 0.50 AVDD + 0.50 −64 −62 −60 −55 −55 −89 −91 −93 −87 −89 −91 −85 −87 −89 −83 −85 −87 Rev Page AD9956 Unit Test Conditions/Comments V V µ µA µ µs ns µs µs ns Bits µ dBc ...
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... AD9956 Parameter 160 MHz Analog Out (±1 MHz) 160 MHz Analog Out (±250 kHz) 160 MHz Analog Out (±50 kHz) DAC Residual Phase Noise 19.7 MHz F OUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 51 ...
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... Rev Page AD9956 Test Conditions/Comments rms OC1, RF Divider rms OC3, RF Divider rms OC12, RF Divider Divider Divider Divider See the Loop Measurement Condi- tions section ...
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... Measured as peak-to-peak from DRV to DRV . 5 For a 4.02 kΩ resistor from DRV_RSET to GND. 6 Assumes load. 7 I/O_UPDATE/PS<2:0> are detected by the AD9956 synchronous to the rising edge of SYNC_CLK. Each latency measurement is from the first SYNC_CLK rising edge after the I/O_UPDATE/PS<2:0> state change. Min Typ Max Unit ...
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... MHz Converter Clock VCO = Sirenza 190-845T Reference = Wenzel 500-10116 (30.3 MHz) Loop Filter = 10 kHz BW, 45° Phase Margin C1 = 117 nF Ω 1.6 µ 57.1 Ω 53.4 nF CP_OUT = 4 mA (Scaler = ×8) ÷ ÷ ÷ INPUT C1 Figure 2. Generic Loop Filter Rev Page AD9956 R2 OUTPUT ...
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... AD9956 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Analog Supply Voltage (AVDD Digital Supply Voltage (DVDD Digital I/O Supply Voltage 3.6 V (DVDD_I/0) 3.6 V Charge Pump Supply Voltage (CPVDD) Maximum Digital Input Voltage −0 DVDD_I/O + 0.5 V Storage Temperature −65°C to +150°C Operating Temperature Range − ...
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... MUST be attached to analog ground. AGND 1 PIN 1 AVDD 2 INDICATOR AGND 3 AVDD 4 IOUT 5 AD9956 IOUT 6 AVDD 7 TOP VIEW (Not to Scale) AGND 8 I/O_RESET 9 RESET 10 DVDD 11 DGND CONNECT Figure 3. 48-Lead LFCSP Pin Configuration Rev Page AD9956 36 CP_OUT 35 CP_VDD 34 AGND 33 DRV 32 DRV 31 CP_VDD 30 AGND 29 REFCLK 28 REFCLK 27 AVDD 26 AGND 25 DVDD ...
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... AD9956 Table 3. 48-Lead LFCSP Pin Function Description Pin No. Mnemonic 26, 30, AGND 34, 37, 43 27, 38, AVDD 44 IOUT 6 IOUT 9 I/O_RESET 10 RESET 11, 25 DVDD 12, 24 DGND 13 SDO 14 SDI/O 15 SCLK DVDD_I/O 18 SYNC_OUT 19 PLL_LOCK/SYNC_IN 20 I/O_UPDATE PS0 to PS2 28 REFCLK 29 REFCLK 32 DRV 33 DRV 31, 35 CP_VDD 36 CP_OUT 39 PLLREF 40 PLLREF 41 PLLOSC ...
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... RF ATT –62.65dB VBW 10kHz REF LVL 100.20040080MHz SWT 5s UNIT 0dBm START 0Hz 20MHz/ STOP 200MHz Figure 8. AD9956 DAC Performance: 400 MSPS Clock, 40 MHz F , 200 MHz Span OUT DELTA 1 [T1] RBW 10kHz RF ATT REF LVL –48.78dB VBW 10kHz 0dBm –400.80160321kHz SWT 5s UNIT ...
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... RF ATT –56.33dB VBW 10kHz REF LVL –80.96192385MHz SWT 5s UNIT 0dBm 0 1 START 0Hz 20MHz/ STOP 200MHz Figure 13. AD9956 DAC Performance: 400 MSPS Clock, 160 MHz F , 200 MHz Span OUT 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 – ...
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... Figure 21. Total System Phase Noise for 622 MHz OC-12 Clock Rev Page 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 19. RF Divider and CML Driver Residual Phase Noise (2488 MHz In, 622 MHz Out) 100 1k 10k 100k 1M FREQUENCY (Hz) 100 1k 10k 100k 1M FREQUENCY (Hz) AD9956 100M 10M 10M ...
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... Figure 22. Dual-Clock Configuration PLLREF CP_OUT LPF PLLOSC DAC DDS LPF AD9956 Figure 23. Fractional-Divider Loop DAC DDS CML DRIVER ÷R AD9956 PLLREF CP_OUT VCO LPF ÷N PLLOSC Figure 24. LO and Baseband Modulation Generation Rev Page CML CLOCK1 CLOCK1′ LPF VCO ÷R ...
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... The DDS can be programmed to output 8 kHz to serve as a base reference for other circuits in the subsystem (see Figure 25). Direct Upconversion The AD9956 is configured to use the DDS as a precision refer- ence to the PLL loop. Since the VCO is < 655 MHz, it can be fed straight into the phase frequency detector feedback input (with the divider enabled), as seen in Figure 26 ...
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... PLL CIRCUITRY The AD9956 includes an RF divider (divide-by-R), a phase frequency detector, and a programmable output current charge pump. Incorporating these blocks together, users can generate many useful circuits for frequency synthesis. A few simple examples are shown in the Typical Application Circuits ...
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... RF divider input • RF divider output • PLLOSC input RISING EDGE SURGE I(t) ~250ps Figure 27. Rising Edge and Falling Edge Surge Current Output of the CML Clock Driver, as Opposed to the Steady State Continuous Current Rev Page AD9956 CONTINUOUS CONTINUOUS FALLING EDGE SURGE t ~250ps ...
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... It is important to note that the synchronization functions included on the AD9956 control only the timing relationships among different digital clocks. They do not compensate for the analog timing skew on the system clock due to mismatched phase relationships on the input clock, REFCLK ...
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... SYNCHRONIZATION FUNCTIONS CAN ALIGN DIGITAL CLOCK RELATIONSHIPS, THEY CANNOT DESKEW THE EDGES OF CLOCKS SYSCLK DUT 1 SYNC CLK DUT1 SYSCLK DUT 2 SYNC CLK DUT2 WITHOUT SYNC_CLK ALIGNED SYNC CLK DUT2 WITH SYNC_CLK ALIGNED Figure 28. Synchronization Functions: Capabilities and Limitations Rev Page AD9956 ...
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... All data input to the AD9956 is registered on the rising edge of SCLK. All data is driven out of the AD9956 on the falling edge of SCLK. Figure 29 through Figure 32 are useful in understand- ing the general operation of the AD9956 serial port. ...
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... For MSB first operation, all data written to (read from) the AD9956 are in MSB first order. If the LSB mode is active, all data written to (read from) the AD9956 are in LSB first order. CS ...
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... SDI/O Open Open Open Input Only PFD Input PLLREF SYNC_CLK Auto Sync Power- Crystal Disable Multiple Down Enable AD9956s Open 1 Open 1 Open 1 Open Clock Driver Falling Edge Control <28:26> RF Divider Ratio Clock Clock Driver Input <22:21> Driver Select <19:18> Power- Down ...
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... Bit 0 Default Value/ Bit 3 Bit 2 Bit 1 (LSB) Profile 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 AD9956 ...
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... AD9956 Register Name Bit (MSB) (Serial Address) Range Bit 7 Profile Control <63:56> Register <55:48> No. 4 (PCR4) (0x0A) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Profile Control <63:56> Register <55:48> No. 5 (PCR5) (0x0B) <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> Profile Control <63:56> Register < ...
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... This control register is comprised of four bytes, all of which must be written during a write operation involving CFR1. CFR1 is used to control various functions, features, and operating modes of the AD9956. The functionality of each bit(s) is described below. In general, the bit is named for the function it serves when the bit is set. ...
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... CFR1<15> Serial data transfer to the device is in LSB first mode. CFR1<14> SDI/O Input Only (3-Wire Serial Data Mode) The serial port on the AD9956 can act in 2-wire mode (SCLK and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit toggles the serial port between these two modes. ...
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... CFR2 primarily controls analog and tim- ing functions on the AD9956. CFR2<39> DAC Power-Down Bit This bit powers down the DAC portion of the AD9956 and puts it into the lowest power dissipation state. CFR2<39> (default). DAC is powered on and operating. CFR2<39> DAC is powered down and the output high impedance state. CFR2< ...
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... AD9956 CFR2<28:26> Clock Driver Falling Edge Control These bits control the slew rate of the CML clock driver output’s falling edge. When these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability. Table 7 describes how the bits increase the current; the contri- butions of each bit are cumulative ...
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... PLL Circuitry section). However possible to multiply the charge pump output current by a value from 1:8 by programming these bits. The charge pump output current is scaled by CFR2<2:0> +1. CFR2<2:0> = 000 (default). Scale factor = 1 to CFR2<2:0> = 111 (8). CFR2<2:0> 000 001 010 011 100 101 110 111 Rev Page AD9956 Scale Factor ...
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... ORDERING GUIDE Model Temperature Range 1 AD9956YCPZ –40°C to +125°C 1 AD9956YCPZ-REEL –40°C to +125°C AD9956/PCB AD9956-VCO/PCB Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 7.00 BSC SQ 0.60 MAX 36 TOP 6 ...