AD9510-VCO/PCB Analog Devices Inc, AD9510-VCO/PCB Datasheet
AD9510-VCO/PCB
Specifications of AD9510-VCO/PCB
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AD9510-VCO/PCB Summary of contents
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... The AD9510 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9510 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is − ...
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... AD9510 TABLE OF CONTENTS Specifications..................................................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 5 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Phase Noise .......................................................... 9 Clock Output Additive Time Jitter........................................... 12 PLL and Distribution Phase Noise and Spurious................... 14 Serial Control Port ..................................................................... 15 FUNCTION Pin ......................................................................... 15 STATUS Pin ................................................................................ 16 Power............................................................................................ 16 Timing Diagrams............................................................................ 17 Absolute Maximum Ratings.......................................................... 18 Thermal Characteristics ...
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... Changes to SYNCB: 58h<6:5> = 01b Section..............................33 Changes to CLK1 and CLK2 Clock Inputs Section....................33 Register Map Description ..........................................................49 Power Supply ...................................................................................56 Power Management ....................................................................56 Applications .....................................................................................57 Using the AD9510 Outputs for ADC Clock Applications ....57 CMOS Clock Distribution.........................................................57 LVPECL Clock Distribution......................................................58 LVDS Clock Distribution...........................................................58 Power and Grounding Considerations and Power Supply Rejection.......................................................................................58 Outline Dimensions ...
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... AD9510 SPECIFICATIONS Typical (typ) is given for V = 3.3 V ± 5 Minimum (min) and maximum (max) values are given over full V PLL CHARACTERISTICS Table 1. Parameter REFERENCE INPUTS (REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFINB Input Resistance, REFIN Input Resistance, REFINB ...
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... Approximation of the PFD/CP phase noise floor (in the flat region) inside the PLL loop bandwidth. When running closed loop this 3 phase noise is gained × log(N) Signal available at STATUS pin when selected by 08h<5:2>. Selected by Register ODh. <5> = 1b. <5> = 0b. <5> = 0b. Selected by Register ODh. <5> = 1b. <5> = 0b. <5> = 0b. AD9510 . ...
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... AD9510 CLOCK OUTPUTS Table 3. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2, OUT3; Differential Output Frequency Output High Voltage ( Output Low Voltage ( Output Differential Voltage ( LVDS CLOCK OUTPUTS OUT4, OUT5, OUT6, OUT7; Differential Output Frequency Differential Output Voltage ( Delta V OD Output Offset Voltage (V ...
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... Delay off on OUT5 and OUT6 ns ns ps/°C Delay off on OUT5 and OUT6 Everything the same; different logic type ns LVPECL to LVDS on same part Everything the same; different logic type ns LVPECL to CMOS on same part Everything the same; different logic type ps LVDS to CMOS on same part AD9510 ...
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... AD9510 Parameter 4 DELAY ADJUST 5 Shortest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL 5 Longest Delay Range Zero Scale Full Scale Linearity, DNL Linearity, INL Delay Variation with Temperature 6 Long Delay Range Zero Scale Full Scale Short Delay Range Zero Scale ...
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... Rev Page AD9510 Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO Input slew rate > 1 V/ns ...
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... AD9510 Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = Offset @ 100 Hz Offset @ 1 kHz Offset ...
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... Rev Page AD9510 Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO ...
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... AD9510 CLOCK OUTPUT ADDITIVE TIME JITTER Table 6. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT3) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT3) = 155.52 MHz Divide Ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT3) = 100 MHz ...
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... Calculated from SNR of ADC method 100 MHz with A C Interferer(s) Interferer(s) 374 fs rms Calculated from SNR of ADC method 100 MHz with A C Interferer(s) Interferer(s) Rev Page AD9510 = 170 MHz IN = 170 MHz IN = 170 MHz IN = 170 MHz IN = 170 MHz IN = 170 MHz IN = 170 MHz IN ...
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... AD9510 Parameter CLK1 = 400 MHz Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz All Other CMOS = 50 MHz (B Output On) 1 DELAY BLOCK ADDITIVE TIME JITTER 100 MHz Output Delay (1600 μA, 1C) Fine Adj. 00000 Delay (1600 μA, 1C) Fine Adj. 11111 Delay (800 μ ...
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... This pin should normally be held high. Do not leave NC. V 0.8 V μA 1 μ High speed clock cycles High speed clock is CLK1 or CLK2, whichever is being used for distribution Rev Page Unit Test Conditions/Comments CSB and SCLK have 30 kΩ internal pull-down resistors V V μA μ MHz AD9510 ...
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... AD9510 STATUS PIN Table 10. Parameter Min OUTPUT CHARACTERISTICS Output Voltage High (V ) 2.7 OH Output Voltage Low ( MAXIMUM TOGGLE RATE ANALOG LOCK DETECT Capacitance POWER Table 11. Parameter POWER-UP DEFAULT MODE POWER DISSIPATION Power Dissipation Power Dissipation Power Dissipation Full Sleep Power-Down Power-Down (PDB) ...
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... TIMING DIAGRAMS t CLK1 CLK1 t PECL t LVDS t CMOS Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 20% SINGLE-ENDED 20 Rev Page 80% LVDS Figure 4. LVDS Timing, Differential 80% CMOS 3pF LOAD Figure 5. CMOS Timing, Single-Ended Load AD9510 ...
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... AD9510 ABSOLUTE MAXIMUM RATINGS Table 12. With Respect to Parameter or Pin VS GND VCP GND VCP V S REFIN, REFINB GND RSET GND CPRSET GND CLK1, CLK1B, CLK2, CLK2B GND CLK1 CLK1B CLK2 CLK2B SCLK, SDIO, SDO, CSB GND OUT0, OUT1, OUT2, OUT3 GND OUT4, OUT5, OUT6, OUT7 ...
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... GND. REFIN 1 PIN 1 INDICATOR REFINB 2 GND VCP GND 7 AD9510 GND 8 TOP VIEW VS 9 (Not to Scale) CLK2 10 CLK2B 11 GND CLK1 14 CLK1B 15 16 Figure 6. 64-Lead LFCSP Pin Configuration Rev Page AD9510 OUT4 46 OUT4B OUT5 42 OUT5B OUT6 38 OUT6B OUT2 34 OUT2B 33 VS ...
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... AD9510 Table 13. Pin Function Descriptions Pin No. Mnemonic Description 1 REFIN PLL Reference Input. 2 REFINB Complementary PLL Reference Input 12, 22, GND Ground. 27, 32, 49, 50, 55 13, 23, 26, VS Power Supply (3 30, 31, 33, 36, 37, 40, 41, 44, 45, 48, 51, 52, 56, 59, 60 VCP Charge Pump Power Supply VCP for VCOs requiring extended tuning range. ...
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... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9510 ...
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... AD9510 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 4 LVPECL + 4 LVDS (DIV ON) 0.7 4 LVPECL + 4 LVDS (DIV BYPASSED) 0.6 0.5 DEFAULT–3 LVPECL + 2 LVDS (DIV ON) 0.4 4 LVDS ONLY (DIV ON) 0.3 4 LVPECL ONLY (DIV ON) 0.2 0 400 OUTPUT FREQUENCY (MHz) Figure 7. Power vs. Frequency—LVPECL, LVDS (PLL Off) CLK1 (EVAL BOARD) ...
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... Figure 17. Charge Pump Output Characteristics @ VCPs = 5.0 V Rev Page 30kHz/ SPAN 300kHz 1 10 PFD FREQUENCY (MHz) PUMP DOWN PUMP UP 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOLTAGE ON CP PIN (V) AD9510 100 4.5 5.0 ...
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... AD9510 VERT 500mV/DIV Figure 18. LVPECL Differential Output @ 800 MHz VERT 100mV/DIV Figure 19. LVDS Differential Output @ 800 MHz VERT 500mV/DIV Figure 20. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 1.8 1.4 1.4 1.4 1.4 1.4 1.4 100 HORIZ 500ps/DIV Figure 21. LVPECL Differential Output Swing vs. Frequency ...
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... Figure 28. Additive Phase Noise—LVDS DIV2, 122.88 MHz –100 –110 –120 –130 –140 –150 –160 –170 1M 10M 10 Figure 29. Additive Phase Noise—CMOS DIV4, 61.44 MHz Rev Page AD9510 100 1k 10k 100k 1M OFFSET (Hz) 100 1k 10k 100k 1M OFFSET (Hz) 100 1k 10k 100k 1M ...
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... TYPICAL MODES OF OPERATION PLL WITH EXTERNAL VCXO/VCO FOLLOWED BY CLOCK DISTRIBUTION This is the most common operational mode for the AD9510. An external oscillator (shown as VCO/VCXO) is phase locked to a reference input frequency applied to REFIN. The loop filter is usually a passive design. A VCO or a VCXO can be used. The CLK2 input is connected internally to the feedback divider, N ...
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... PUMP N FUNCTION STATUS CLK1 CLK2 LVPECL DIVIDE LVPECL DIVIDE LVPECL DIVIDE LVPECL SERIAL DIVIDE PORT LVDS/CMOS DIVIDE LVDS/CMOS Δ DIVIDE T LVDS/CMOS Δ DIVIDE T LVDS/CMOS DIVIDE Figure 32. AD9510 with VCO and BPF Filter Rev Page AD9510 LOOP FILTER VCO BPF CLOCK OUTPUTS ...
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... AD9510 REFIN 250MHz REFINB FUNCTION CLK1 1.6GHz CLK1B SCLK SDIO SDO CSB VS GND RSET DISTRIBUTION AD9510 REF R DIVIDER PHASE FREQUENCY DETECTOR N DIVIDER SYNCB, RESETB, PDB PROGRAMMABLE DIVIDERS AND PHASE ADJUST /1, /2, /3... /31, /32 /1, /2, /3... /31, /32 /1, /2, /3... /31, /32 SERIAL CONTROL /1, /2, /3... /31, /32 PORT /1, /2, /3 ...
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... PFD frequency. See Figure 34. VCO/VCXO Feedback Divider—N ( The N divider is a combination of a prescaler bits) and two counters bits) and B (13 bits). Although the AD9510’s PLL is similar to the ADF4106, the AD9510 has a redesigned prescaler that allows lower values of N. The prescaler has both a dual modulus (DM) and a fixed divide (FD) mode ...
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... Mode (DM = Dual Modulus (2/ (4/ (8/ and B Counters The AD9510 B counter has a bypass mode (B = 1), which is not available on the ADF4106. The B counter bypass mode is valid Divide By only when using the prescaler in FD mode. The B counter is 1 bypassed by writing 1 to the B counter bypass bit (0Ah<6> 1b) ...
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... VCO signal. STATUS Pin The output multiplexer on the AD9510 allows access to various signals and internal points on the chip at the STATUS pin. Figure 37 shows a block diagram of the STATUS pin section. The function of the STATUS pin is controlled by Register 08h< ...
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... PLL MUX CONTROL 08h <5:2> Figure 37. STATUS Pin Circuit CLK1 Clock Input The digital lock detect (DLD) block of the AD9510 requires a PLL reference signal to be present in order for the digital lock detect output to be valid possible to have a digital lock detect indication (DLD = true) that remains true even after a loss-of-reference signal ...
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... DIVIDERS Each of the eight clock outputs of the AD9510 has its own divider. The divider can be bypassed to get an output at the same frequency as the input (1×). When a divider is bypassed powered down to save power ...
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... AD9510 Setting the Divide Ratio The divide ratio is determined by the values written via the SCP to the registers that control each individual output, OUT0 to OUT7. These are the even numbered registers beginning at 48h and going through 56h. Each of these registers is divided into bits that control the number of clock cycles that the divider output stays high (high_cycles < ...
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... LO <7:4> Divide Ratio Duty Cycle (%) 48h to 56h HI<3:0> Divide Ratio Rev Page AD9510 48h to 56h LO <7:4> HI<3:0> Duty Cycle (%) ...
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... AD9510 LO <7:4> Divide Ratio Duty Cycle (%) 48h to 56h HI<3:0> Divide Ratio Rev Page 48h to 56h LO <7:4> HI<3:0> Duty Cycle (%) ...
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... LO <7:4> Divide Ratio Duty Cycle (%) 48h to 56h HI<3:0> Divide Ratio Rev Page AD9510 48h to 56h LO <7:4> HI<3:0> Duty Cycle (%) ...
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... AD9510 Divider Phase Offset The phase of each output may be selected, depending on the divide ratio chosen. This is selected by writing the appropriate values to the registers which set the phase and start high/low bit for each output. These are the odd numbered registers from 49h to 57h. Each divider has a 4-bit phase offset < ...
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... Fine_Adj = Value of Delay Fine Adjust (Register 36h or Register 3Ah <5:1>), that is, 11111 = 31 Delay (ns) = Offset + Delay_Range × Fine_adj × (1/31) OUTPUTS The AD9510 offers three different output level choices: LVPECL, LVDS, and CMOS. OUT0 to OUT3 are LVPECL only. LVDS OUT4 to OUT7 can be selected as either LVDS or CMOS. Each output can be enabled or turned off as needed to save power ...
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... POWER-DOWN MODES Chip Power-Down or Sleep Mode—PDB The PDB chip power-down turns off most of the functions and currents in the AD9510. When the PDB mode is enabled, a chip power-down is activated by taking the FUNCTION pin to a logic low level. The chip remains in this power-down state until PDB is brought back to logic high ...
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... This clock must be no faster than one-fourth of the fast clock, and no greater than 250 MHz. The slow clock is taken from one of the outputs of the master AD9510 and acts as the REFIN (or CLK2) input to the slave AD9510. One of the outputs of the slave must provide this same frequency back to the CLK2 (or REFIN) input of the slave ...
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... If the instruction word is for a write operation (I15 = 0b), the second part is the transfer of data into the serial control port buffer of the AD9510. The length of the transfer ( bytes, or streaming mode) is indicated by 2 bits (W1:W0) in the instruction byte. CSB can be raised after each sequence of 8 bits to stall the bus (except after the last byte, where it ends the cycle) ...
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... MSB/LSB FIRST TRANSFERS The AD9510 instruction word and byte data may be MSB first or LSB first. The default for the AD9510 is MSB first. The LSB first mode may be set by writing 1b to Register 00h<6>. This takes effect immediately (since it only affects the operation of the serial control port) and does not require that an update be executed ...
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... AD9510 Table 21. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 I11 A12 = 0 A11 = 0 CSB SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 46. Serial Control Port Write—MSB First, 16-Bit Instruction, 2 Bytes Data ...
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... TIMING DIAGRAM FOR TWO SUCCESSIVE CUMMUNICATION CYCLES. NOTE THAT CSB MUST BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OF A COMMUNICATION CYCLE. t CLK Figure 51. Serial Control Port Timing—Write CSB TOGGLE INDICATES CYCLE COMPLETE t PWH 16 INSTRUCTION BITS + 8 DATA BITS COMMUNICATION CYCLE 2 Figure 52. Use of CSB to Define Communications Cycle Rev Page AD9510 t H ...
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... AD9510 REGISTER MAP AND DESCRIPTION SUMMARY TABLE Table 23. AD9510 Register Map Addr (Hex) Parameter Bit 7 (MSB) 00 Serial SDO Inactive Control Port (Bidirectional Configuration Mode PLL 04 A Counter Not Used 05 B Counter Not Used 06 B Counter 07 PLL 1 Not Used 08 PLL 2 Not Used ...
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... Phase Offset <3:0> 00 High Cycles <3:0> 33 Phase Offset <3:0> 00 High Cycles <3:0> 00 Phase Offset <3:0> 00 High Cycles <3:0> 11 Phase Offset <3:0> 00 High Cycles <3:0> 00 AD9510 Notes Min. Delay Value OFF LVDS, ON LVDS, ON LVDS, OFF LVDS, OFF Input Receivers All Clocks ON, Select ...
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... AD9510 Addr (Hex) Parameter Bit 7 (MSB) 55 Divider 6 Bypass 56 Divider 7 57 Divider 7 Bypass FUNCTION 58 FUNCTION Not Used Pin and Sync 59 5A Update Registers END Bit 6 Bit 5 Bit 4 Bit 3 No Force Start H/L Sync Low Cycles <7:4> No Force Start H/L Sync Set FUNCTION Pin ...
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... REGISTER MAP DESCRIPTION Table 24 lists the AD9510 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 24 describes the functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 23. ...
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... AD9510 Reg. Addr. (Hex) Bit(s) Name Description 08 <5:2> PLL Mux Control <5> MUXOUT is the PLL portion of the STATUS output MUX 08 <6> Phase-Frequency 0 = Negative (Default Positive Detector (PFD) Polarity 08 <7> Not Used 09 <0> Reset All Counters 0 = Normal (Default Reset R, A, and B Counters 09 < ...
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... The slowest ramp (200 μA) sets the longest full scale of approximately 10 ns. <3> <2> Mode Prescaler Mode Divide Divide 16/ 32/ Divide by 3 <0> Antibacklash Pulse Width (ns) 0 1.3 (Default) 1 2.9 0 6.0 1 1.3 Digital Lock Detect Window (ns) 9.5 3.5 Rev Page Digital Lock Detect Loss-of-Lock Threshold (ns AD9510 ...
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... AD9510 Reg. Addr. (Hex) Bit(s) Name Description (39) (OUT6) <2> <5:3> Ramp Capacitor Selects the Number of Capacitors in Ramp Generation Circuit 35 OUT5 More Capacitors => Slower Ramp (39) (OUT6) <5> <5:1> Delay Fine Adjust 36 OUT5 Sets Delay Within Full Scale of the Ramp; There are 32 Steps ...
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... Disable Inverted CMOS Driver (Default Enable Inverted CMOS Driver 40 OUT4 (41) (OUT5) (42) (OUT6) (43) (OUT7) 40 <7:5> Not Used (41) (42) (43) 44 <7:0> Not Used <2> <1> Current (mA) 0 1.75 1 3.5 (Default Rev Page AD9510 Output Voltage (mV) 500 340 810 (Default) 660 Termination (Ω) 100 100 50 50 ...
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... AD9510 Reg. Addr. (Hex) Bit(s) Name Description 45 <0> Clock Select 0: CLK2 Drives Distribution Section 1: CLK1 Drives Distribution Section (Default) 45 <1> CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b) 45 <2> CLK2 Power-Down 1 = CLK2 Input Is Powered Down (Default = 0b) 45 <3> Prescaler Clock 1 = Shut Down Clock Signal to PLL Prescaler (Default = 0b) ...
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... A 1 written to this bit updates all registers and transfers all serial control port register buffer contents to the control registers on the next rising SCLK edge. This is a self-clearing bit does not have to be written to clear it. 5A <7:1> Not Used END <5> Rev Page AD9510 Function RESETB (Default) SYNCB Test Only; Do Not Use PDB ...
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... AD9510; therefore, this GND connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the PCB. See the layout of the AD9510 evaluation board (AD9510/PCB or AD9510-VCO/PCB) for a good example. POWER MANAGEMENT The power usage of the AD9510 can be managed to use only the power required for the functions that are being used ...
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... Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9510 do not supply enough 6 current to provide a full voltage swing with a low impedance 4 resistive, far-end termination, as shown in Figure 55. The 30 100 far-end termination network should match the PCB trace impedance and provide the desired switching point ...
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... Figure 57. LVPECL with Parallel Transmission Line LVDS CLOCK DISTRIBUTION Low voltage differential signaling (LVDS second differential output option for the AD9510. LVDS uses a current mode output stage with several user-selectable current levels. The normal value (default) for this current is 3.5 mA, which yields 350 mV output swing across a 100 Ω ...
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... MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9510BCPZ −40°C to +85°C 1 AD9510BCPZ-REEL7 −40°C to +85°C AD9510/PCB AD9510-VCO/PCB Pb-free part. 0.60 MAX 49 48 8.75 BSC SQ 0.45 0. 0.35 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM ...
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... AD9510 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05046–0–5/05(A) Rev Page ...