AD9480-LVDS/PCB Analog Devices Inc, AD9480-LVDS/PCB Datasheet
AD9480-LVDS/PCB
Specifications of AD9480-LVDS/PCB
Related parts for AD9480-LVDS/PCB
AD9480-LVDS/PCB Summary of contents
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... CLK– LOGIC PDWN S1 LVDSBIAS Figure 1. PRODUCT HIGHLIGHTS 1. Superior linearity. A DNL of ±0.25 makes the AD9480 suitable for instrumentation and measurement applications. 2. Power-down mode. A power-down function may be exercised to bring total consumption down to 15 mW. 3. LVDS outputs (ANSI-644). LVDS outputs simplify timing and improve noise performance One Technology Way, P ...
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... Changes to Analog Inputs ............................................................. 16 Changes to Figure 30...................................................................... 16 Added Power Down Section ......................................................... 18 Changes to Table 12........................................................................ 21 7/04—Revision 0: Initial Version Interleaving Two AD9480s........................................................ 18 Data Clock Out........................................................................... 18 Power-Down ............................................................................... 18 AD9480 Evaluation Board ............................................................ 19 Power Connector........................................................................ 19 Analog Inputs ............................................................................. 19 Gain.............................................................................................. 19 Optional Operational Amplifier .............................................. 19 Clock ............................................................................................ 19 Optional Clock Buffer ............................................................... 19 Optional XTAL ........................................................................... 19 Voltage Reference ...
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... Figure 13 for active operation. AD9480 Unit Bits LSB LSB LSB µV/°C %FS/°C mV/° µA µA V p-p V kΩ kΩ pF MHz mV/V ...
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... Full VI 4.2 25°C V Full IV 2.0 Full IV Full VI Full VI 25°C V 25°C V Full VI 247 Full VI 1.125 Full IV Rev Page AD9480-250 Typ Max Unit mV p-p 1.5 1.68 V 5.5 6.0 kΩ 0.8 V ±160 µA 10 µA 30 kΩ 454 mV 1.375 V Twos complement or binary ...
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... I 44.8 46.5 I 44.8 46.5 V 7.6 I 7.3 7.6 I 7.3 7.6 V −65 I −65 −60 I −65 −60 V −70 I −70 −63 I −70 −63 V −65 I −65 −60 I −65 −60 V −68 AD9480 Unit Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... VI 25°C V 25° equals 5 pF maximum. PD LOAD N+1 N+8 8 CYCLES 1 N–8 N–7 Figure 2. Timing Diagram Rev Page AD9480-250 Min Typ Max 250 20 1.2 2 1.2 2 1.9 2.8 3.8 0.5 0.5 1.9 2.7 3.7 0 0.1 0.6 8 1.5 0.25 N+10 N+11 ...
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... V section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect +0.5 V device reliability. DRVDD + 0.5 V AVDD + 0.5 V 85°C 150°C 150°C 150°C Rev Page AD9480 ...
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... D5_C Data Output Bit 5—Complement 22 D5_T Data Output Bit 5—True 1 Pin 43 will self-bias to 1 can be left floating (as recommended) or tied to AVDD or ground with no ill effects CLK+ 1 PIN 1 CLK– 2 AVDD 3 AGND 4 AD9480 DRVDD 5 TOP VIEW (Not to Scale) DRGND D1_C 9 D1_T 10 D2_C Figure 3. Pin Configuration Pin No ...
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... Logic 1 state to achieve rated performance; pulse width low is the minimum time that the clock pulse should be left in a low state. See the timing implications of changing t in the Clocking the AD9480 EH section given clock rate, these specifications define an acceptable clock duty cycle. ...
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... AD9480 Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc ...
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... MHz @ −1 dBFS SFDR 100 150 200 250 A (MHz −1 dBFS SFDR 100 150 200 250 A (MHz) IN Figure 9. Analog Input Frequency Sweep 0. 250 MSPS S AD9480 100 120 SNR SINAD 300 350 400 = 250 MSPS S H2 SNR SINAD 300 350 400 = −1 dBFS, ...
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... AD9480 SFDR SNR 45 SINAD 100 150 SAMPLE CLOCK (MHz) Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency SFDRdBFS SFDRdBc 10 65dB REF LINE 0 –70 –60 –50 –40 –30 ANALOG INPUT DRIVE LEVEL (dBFS) Figure 11. SFDR vs. A Input Level F1 –7dBFS 2F2-F1 = –71.1dBc –10 2F1-F2 = –68dBc – ...
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... AVDD (V) Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage 70.3 MHz @ −1 dBFS, 250 MSPS 100 150 CODE = 10.3 MHz @ –0.5 dBFS, 250 MSPS 100 150 CODE = 10.3 MHz @ −0.5 dBFS, 250 MSPS IN AD9480 3.5 3.6 200 250 200 250 ...
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... AD9480 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –40 – TEMPERATURE (°C) Figure 22. Propagation Delay Adder vs. Temperature 900 800 700 600 500 400 300 200 100 Figure 23. LVDS Output Swing, Common-Mode Voltage vs. RSET, Rev Page RSET (kΩ) Placed at LVDSBIAS 1.4 1 ...
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... CLK– 150Ω 10kΩ VDD Rev Page PDWN 30kΩ Figure 27. Power-Down Input DRVDD 1.2V LVDSBIAS 3.7kΩ Figure 28. LVDSBIAS Input DRVDD V+ V– DX+ DX– V– V+ Figure 29. LVDS Data, DCO Outputs AD9480 AVDD DRVDD K ILVDS OUT ...
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... AVDD ± (0.1 × AVDD) AGND −> (0.1 × AVDD) ANALOG INPUTS The analog input to the AD9480 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN− should match. Optimal performance is obtained when the analog inputs are driven differentially. SNR and SINAD performance can degrade if the analog input is driven with a single-ended signal ...
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... DIGITALOUT = ALL 0s Figure 33. Analog Input Full Scale VOLTAGE REFERENCE A stable and accurate 1.0 V reference is built into the AD9480. Users can choose this internal reference or provide an external reference for greater accuracy and flexibility. Figure 35 shows the typical reference variation with temperature. Table 9 summarizes the available reference configurations ...
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... V INTERLEAVING TWO AD9480s Instrumentation applications may prefer to interleave or ping- pong two AD9480s to achieve twice the sample rate, or 500 MSPS. In these applications important to match the gain and offset of the two ADCs. Varying the reference voltage allows the gain of the ADCs to be adjusted; external dc offset compensation can be used to reduce offset mismatch between two ADCs ...
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... AD9480 EVALUATION BOARD The AD9480 evaluation board offers an easy way to test the device. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC and a data-ready signal. The digital outputs and output clocks are available at a 40-pin connector, P10 ...
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... AD9480 VOLTAGE REFERENCE The AD9480 has an internal 1 V reference mode. The ADC uses the internal 1 V reference as the default when SENSE is set to ground. An optional on-board external 1.0 V reference (ADR510) can be used by setting the SENSE jumper to AVDD, by placing a jumper on E20 to E3, and by placing a 0 Ω resistor on R36 ...
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... Resistors Resistors Resistor Transformer AD8351 SN65LVDS1 ADR510 VCC6PECL6 XO-400 AD9480 MC100LVEL16D ETC1-1-13 Capacitors Resistors Jumpers Output Data Connector Rev Page AD9480 Package Value 0402 0.1 µF Tantalum (3528) 10 µF Tantalum (6032) 10 µF Z5.531.3425.0 Wieland 25.602.5453.0 Wieland 0603 50 Ω 0603 100 Ω ...
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... AD9480 PCB SCHEMATICS 1 P1 GND 2 P2 VAMP 3 P3 GND 4 DRVDD P4 1 GND P1 2 AVDD P2 3 GND VCTRL GND S1 PWDN GND AVDD GND D6C D2C D6T D1T D1C D7C D7T D0T DRGND D0C 1 S DRGND PWDN DRVDD AGND AGND AVDD AVDD AGND CLK– ...
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... Figure 42. PCB Schematic ( Rev Page AD9480 ...
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... AD9480 PCB LAYERS Figure 43. PCB Top-Side Silkscreen Figure 44. PCB Top-Side Copper Routing Figure 45. PCB Ground Layer Figure 46. PCB Split Power Plane Rev Page ...
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... Figure 47. PCB Bottom-Side Copper Routing Figure 48. PCB Bottom-Side Silkscreen Rev Page AD9480 ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range −40 ° +85 ° C AD9480BSUZ-250 1, 2 −40 ° +85 ° AD9480ASUZ-250 3 AD9480-LVDS/PCB Pb-free part. 2 Optimized differential nonlinearity. 3 Evaluation board shipped with AD9480BSUZ-250 installed. 1.20 MAX 0.75 44 0.60 1 0.45 0° MIN 0.20 0.09 7° ...
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... NOTES Rev Page AD9480 ...
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... AD9480 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04619–0–4/05(A) Rev Page ...