EVAL-ADG2188EB | |
|---|---|
| Manufacturer Part Number | EVAL-ADG2188EB |
| Description | BOARD EVAL FOR ADG2188 |
| Manufacturer | Analog Devices Inc |
| EVAL-ADG2188EB datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
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Specifications of EVAL-ADG2188EB | |||
|---|---|---|---|
| Module/board Type | Evaluation Board | For Use With/related Products | ADG2188 |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | ||
PrevNext
ADG2188
1
Parameter
Conditions
t
Standard mode
11
Fast mode
2
High speed mode
C
= 100 pF maximum
B
C
= 400 pF maximum
B
t
Standard mode
11A
Fast mode
2
High speed mode
C
= 100 pF maximum
B
C
= 400 pF maximum
B
t
Standard mode
12
Fast mode
2
High speed mode
C
= 100 pF maximum
B
C
= 400 pF maximum
B
t
Fast mode
SP
2
High speed mode
1
Guaranteed by initial characterization. All values measured with input filtering enabled. C
0.3 V
and 0.7 V
.
DD
DD
2
2
High speed I
C is available only in -HS models
3
A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
t
11
t
2
SCL
t
6
SDA
t
7
S
P
S = START CONDITION
P = STOP CONDITION
ADG2188 Limit at T
, T
MIN
MAX
Min
Max
Unit
Description
1000
ns
t
RCL
20 + 0.1 C
300
ns
B
10
40
ns
20
80
ns
1000
ns
t
RCL1
20 + 0.1 C
300
ns
B
10
80
ns
20
160
ns
300
ns
t
FCL
20 + 0.1 C
300
ns
B
10
40
ns
20
80
ns
0
50
ns
Pulse width of suppressed spike
0
10
ns
refers to capacitive load on the bus line; t
B
t
12
t
t
3
4
t
1
Figure 2. Timing Diagram for 2-Wire Serial Interface
Rev. 0 | Page 8 of 28
, rise time of SCL signal
, rise time of SCL signal after a repeated start condition
and after an acknowledge bit
, fall time of SCL signal
and t
are measured between
R
F
t
6
t
t
5
8
t
10
S
t
9
P
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